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| author | Steven Price <steven.price@arm.com> | 2019-12-16 11:56:31 +0000 |
|---|---|---|
| committer | Will Deacon <will@kernel.org> | 2020-01-16 10:44:14 +0000 |
| commit | 275fa0ea2cf7a84450f9c0ec0d9e7ec168ed2e2d (patch) | |
| tree | 1a14bb38c7438a57a0f21266e1f81f5d0aed7186 /arch/arm64/kvm/hyp/tlb.c | |
| parent | db0d46a58d34c7cd9d5ece98daf4b8afe3d770f8 (diff) | |
| download | linux-next-275fa0ea2cf7a84450f9c0ec0d9e7ec168ed2e2d.tar.gz | |
arm64: Workaround for Cortex-A55 erratum 1530923
Cortex-A55 erratum 1530923 allows TLB entries to be allocated as a
result of a speculative AT instruction. This may happen in the middle of
a guest world switch while the relevant VMSA configuration is in an
inconsistent state, leading to erroneous content being allocated into
TLBs.
The same workaround as is used for Cortex-A76 erratum 1165522
(WORKAROUND_SPECULATIVE_AT_VHE) can be used here. Note that this
mandates the use of VHE on affected parts.
Acked-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Steven Price <steven.price@arm.com>
Signed-off-by: Will Deacon <will@kernel.org>
Diffstat (limited to 'arch/arm64/kvm/hyp/tlb.c')
| -rw-r--r-- | arch/arm64/kvm/hyp/tlb.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm64/kvm/hyp/tlb.c b/arch/arm64/kvm/hyp/tlb.c index ff4e73c9bafc..92f560e3e1aa 100644 --- a/arch/arm64/kvm/hyp/tlb.c +++ b/arch/arm64/kvm/hyp/tlb.c @@ -25,8 +25,8 @@ static void __hyp_text __tlb_switch_to_guest_vhe(struct kvm *kvm, if (cpus_have_const_cap(ARM64_WORKAROUND_SPECULATIVE_AT_VHE)) { /* - * For CPUs that are affected by ARM erratum 1165522, we - * cannot trust stage-1 to be in a correct state at that + * For CPUs that are affected by ARM errata 1165522 or 1530923, + * we cannot trust stage-1 to be in a correct state at that * point. Since we do not want to force a full load of the * vcpu state, we prevent the EL1 page-table walker to * allocate new TLBs. This is done by setting the EPD bits |