diff options
| author | Huacai Chen <chenhc@lemote.com> | 2014-06-26 11:41:28 +0800 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2014-07-30 21:46:19 +0200 |
| commit | c46173183657bbdbe0d54a981c28807581648422 (patch) | |
| tree | 554d75cfc577d82c043b3e2fca17819abd63033b /arch/mips/loongson/loongson-3/smp.c | |
| parent | 140e39c1e3d29f50e161f55cca60f60b80408c2a (diff) | |
| download | linux-next-c46173183657bbdbe0d54a981c28807581648422.tar.gz | |
MIPS: Add NUMA support for Loongson-3
Multiple Loongson-3A chips can be interconnected with HT0-bus. This is
a CC-NUMA system that every chip (node) has its own local memory and
cache coherency is maintained by hardware. The 64-bit physical memory
address format is as follows:
0x-0000-YZZZ-ZZZZ-ZZZZ
The high 16 bits should be 0, which means the real physical address
supported by Loongson-3 is 48-bit. The "Y" bits is the base address of
each node, which can be also considered as the node-id. The "Z" bits is
the address offset within a node, which means every node has a 44 bits
address space.
Macros XPHYSADDR and MAX_PHYSMEM_BITS are modified unconditionally,
because many other MIPS CPUs have also extended their address spaces.
Signed-off-by: Huacai Chen <chenhc@lemote.com>
Cc: John Crispin <john@phrozen.org>
Cc: Steven J. Hill <Steven.Hill@imgtec.com>
Cc: Aurelien Jarno <aurelien@aurel32.net>
Cc: linux-mips@linux-mips.org
Cc: Fuxin Zhang <zhangfx@lemote.com>
Cc: Zhangjin Wu <wuzhangjin@gmail.com>
Patchwork: https://patchwork.linux-mips.org/patch/7187/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/loongson/loongson-3/smp.c')
| -rw-r--r-- | arch/mips/loongson/loongson-3/smp.c | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/arch/mips/loongson/loongson-3/smp.c b/arch/mips/loongson/loongson-3/smp.c index 3c320e709e91..ed0e2d0f87ab 100644 --- a/arch/mips/loongson/loongson-3/smp.c +++ b/arch/mips/loongson/loongson-3/smp.c @@ -203,6 +203,8 @@ static void loongson3_init_secondary(void) for (i = 0; i < loongson_sysconf.nr_cpus; i++) loongson3_ipi_write32(0xffffffff, ipi_en0_regs[i]); + cpu_data[cpu].package = cpu / loongson_sysconf.cores_per_package; + cpu_data[cpu].core = cpu % loongson_sysconf.cores_per_package; per_cpu(cpu_state, cpu) = CPU_ONLINE; i = 0; @@ -394,17 +396,19 @@ static int loongson3_cpu_callback(struct notifier_block *nfb, unsigned long action, void *hcpu) { unsigned int cpu = (unsigned long)hcpu; + uint64_t core_id = cpu_data[cpu].core; + uint64_t package_id = cpu_data[cpu].package; switch (action) { case CPU_POST_DEAD: case CPU_POST_DEAD_FROZEN: pr_info("Disable clock for CPU#%d\n", cpu); - LOONGSON_CHIPCFG(0) &= ~(1 << (12 + cpu)); + LOONGSON_CHIPCFG(package_id) &= ~(1 << (12 + core_id)); break; case CPU_UP_PREPARE: case CPU_UP_PREPARE_FROZEN: pr_info("Enable clock for CPU#%d\n", cpu); - LOONGSON_CHIPCFG(0) |= 1 << (12 + cpu); + LOONGSON_CHIPCFG(package_id) |= 1 << (12 + core_id); break; } |