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| author | Alexander Graf <agraf@suse.de> | 2014-04-17 12:53:13 +0200 |
|---|---|---|
| committer | Alexander Graf <agraf@suse.de> | 2014-05-30 14:26:17 +0200 |
| commit | 07fec1c2e75ef2f55d7a211414b0d63e185e84f0 (patch) | |
| tree | f71b012a7ffd10655f37d78a8c9ea39a9b31a07d /arch/powerpc/kvm/e500_emulate.c | |
| parent | 1f854112553a1d65363ab27d4ee3dfb4b27075fb (diff) | |
| download | linux-next-07fec1c2e75ef2f55d7a211414b0d63e185e84f0.tar.gz | |
KVM: PPC: E500: Ignore L1CSR1_ICFI,ICLFR
The L1 instruction cache control register contains bits that indicate
that we're still handling a request. Mask those out when we set the SPR
so that a read doesn't assume we're still doing something.
Signed-off-by: Alexander Graf <agraf@suse.de>
Diffstat (limited to 'arch/powerpc/kvm/e500_emulate.c')
| -rw-r--r-- | arch/powerpc/kvm/e500_emulate.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/powerpc/kvm/e500_emulate.c b/arch/powerpc/kvm/e500_emulate.c index 89b7f821f6c4..95d886f461fb 100644 --- a/arch/powerpc/kvm/e500_emulate.c +++ b/arch/powerpc/kvm/e500_emulate.c @@ -222,6 +222,7 @@ int kvmppc_core_emulate_mtspr_e500(struct kvm_vcpu *vcpu, int sprn, ulong spr_va break; case SPRN_L1CSR1: vcpu_e500->l1csr1 = spr_val; + vcpu_e500->l1csr1 &= ~(L1CSR1_ICFI | L1CSR1_ICLFR); break; case SPRN_HID0: vcpu_e500->hid0 = spr_val; |