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author | Aravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com> | 2016-04-30 14:33:53 +0200 |
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committer | Ingo Molnar <mingo@kernel.org> | 2016-05-03 08:24:16 +0200 |
commit | bb91f8c0176b072aeb6b84cfd7e04084025121e0 (patch) | |
tree | a8eac3f5676531fc7629f04db74ed56b11f2156c /arch/x86/include/asm/mce.h | |
parent | 6bda529ec42e1cd4dde1c3d0a1a18000ffd3d419 (diff) | |
download | linux-next-bb91f8c0176b072aeb6b84cfd7e04084025121e0.tar.gz |
x86/mce: Carve out writes to MCx_STATUS and MCx_CTL
We need to do this after __mcheck_cpu_init_vendor() as for
ScalableMCA processors, there are going to be new MSR write handlers
if the feature is detected using CPUID bit (which happens in
__mcheck_cpu_init_vendor()).
No functional change is introduced here.
Signed-off-by: Aravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com>
Signed-off-by: Yazen Ghannam <Yazen.Ghannam@amd.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Cc: Andy Lutomirski <luto@amacapital.net>
Cc: Aravind Gopalakrishnan <aravindksg.lkml@gmail.com>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Brian Gerst <brgerst@gmail.com>
Cc: Denys Vlasenko <dvlasenk@redhat.com>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Tony Luck <tony.luck@intel.com>
Cc: linux-edac <linux-edac@vger.kernel.org>
Link: http://lkml.kernel.org/r/1462019637-16474-4-git-send-email-bp@alien8.de
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Diffstat (limited to 'arch/x86/include/asm/mce.h')
0 files changed, 0 insertions, 0 deletions