diff options
author | Dmitry Torokhov <dmitry.torokhov@gmail.com> | 2013-03-17 19:40:50 -0700 |
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committer | Dmitry Torokhov <dmitry.torokhov@gmail.com> | 2013-03-17 19:40:50 -0700 |
commit | 688d794c4c3f8b08c814381ee2edd3ede5856056 (patch) | |
tree | ef680add71e2a9588d07d8b594edbc1b5cd127d7 /drivers/bcma | |
parent | 16142655269aaf580488e074eabfdcf0fb4e3687 (diff) | |
parent | a937536b868b8369b98967929045f1df54234323 (diff) | |
download | linux-next-688d794c4c3f8b08c814381ee2edd3ede5856056.tar.gz |
Merge tag 'v3.9-rc3' into next
Merge with mainline to bring in module_platform_driver_probe() and
devm_ioremap_resource().
Diffstat (limited to 'drivers/bcma')
-rw-r--r-- | drivers/bcma/Kconfig | 8 | ||||
-rw-r--r-- | drivers/bcma/Makefile | 1 | ||||
-rw-r--r-- | drivers/bcma/bcma_private.h | 30 | ||||
-rw-r--r-- | drivers/bcma/driver_chipcommon.c | 218 | ||||
-rw-r--r-- | drivers/bcma/driver_chipcommon_nflash.c | 9 | ||||
-rw-r--r-- | drivers/bcma/driver_chipcommon_pmu.c | 48 | ||||
-rw-r--r-- | drivers/bcma/driver_chipcommon_sflash.c | 39 | ||||
-rw-r--r-- | drivers/bcma/driver_gmac_cmn.c | 2 | ||||
-rw-r--r-- | drivers/bcma/driver_gpio.c | 114 | ||||
-rw-r--r-- | drivers/bcma/driver_mips.c | 231 | ||||
-rw-r--r-- | drivers/bcma/driver_pci.c | 4 | ||||
-rw-r--r-- | drivers/bcma/driver_pci_host.c | 101 | ||||
-rw-r--r-- | drivers/bcma/host_pci.c | 14 | ||||
-rw-r--r-- | drivers/bcma/main.c | 84 | ||||
-rw-r--r-- | drivers/bcma/sprom.c | 5 |
15 files changed, 734 insertions, 174 deletions
diff --git a/drivers/bcma/Kconfig b/drivers/bcma/Kconfig index a533af218368..8b4221cfd118 100644 --- a/drivers/bcma/Kconfig +++ b/drivers/bcma/Kconfig @@ -65,6 +65,14 @@ config BCMA_DRIVER_GMAC_CMN If unsure, say N +config BCMA_DRIVER_GPIO + bool "BCMA GPIO driver" + depends on BCMA && GPIOLIB + help + Driver to provide access to the GPIO pins of the bcma bus. + + If unsure, say N + config BCMA_DEBUG bool "BCMA debugging" depends on BCMA diff --git a/drivers/bcma/Makefile b/drivers/bcma/Makefile index 8ad42d41b2f2..734b32f09c0a 100644 --- a/drivers/bcma/Makefile +++ b/drivers/bcma/Makefile @@ -6,6 +6,7 @@ bcma-y += driver_pci.o bcma-$(CONFIG_BCMA_DRIVER_PCI_HOSTMODE) += driver_pci_host.o bcma-$(CONFIG_BCMA_DRIVER_MIPS) += driver_mips.o bcma-$(CONFIG_BCMA_DRIVER_GMAC_CMN) += driver_gmac_cmn.o +bcma-$(CONFIG_BCMA_DRIVER_GPIO) += driver_gpio.o bcma-$(CONFIG_BCMA_HOST_PCI) += host_pci.o bcma-$(CONFIG_BCMA_HOST_SOC) += host_soc.o obj-$(CONFIG_BCMA) += bcma.o diff --git a/drivers/bcma/bcma_private.h b/drivers/bcma/bcma_private.h index 169fc58427d3..79595a001204 100644 --- a/drivers/bcma/bcma_private.h +++ b/drivers/bcma/bcma_private.h @@ -22,7 +22,7 @@ struct bcma_bus; /* main.c */ -int __devinit bcma_bus_register(struct bcma_bus *bus); +int bcma_bus_register(struct bcma_bus *bus); void bcma_bus_unregister(struct bcma_bus *bus); int __init bcma_bus_early_register(struct bcma_bus *bus, struct bcma_device *core_cc, @@ -31,6 +31,8 @@ int __init bcma_bus_early_register(struct bcma_bus *bus, int bcma_bus_suspend(struct bcma_bus *bus); int bcma_bus_resume(struct bcma_bus *bus); #endif +struct bcma_device *bcma_find_core_unit(struct bcma_bus *bus, u16 coreid, + u8 unit); /* scan.c */ int bcma_bus_scan(struct bcma_bus *bus); @@ -45,11 +47,12 @@ int bcma_sprom_get(struct bcma_bus *bus); /* driver_chipcommon.c */ #ifdef CONFIG_BCMA_DRIVER_MIPS void bcma_chipco_serial_init(struct bcma_drv_cc *cc); +extern struct platform_device bcma_pflash_dev; #endif /* CONFIG_BCMA_DRIVER_MIPS */ /* driver_chipcommon_pmu.c */ -u32 bcma_pmu_alp_clock(struct bcma_drv_cc *cc); -u32 bcma_pmu_get_clockcpu(struct bcma_drv_cc *cc); +u32 bcma_pmu_get_alp_clock(struct bcma_drv_cc *cc); +u32 bcma_pmu_get_cpu_clock(struct bcma_drv_cc *cc); #ifdef CONFIG_BCMA_SFLASH /* driver_chipcommon_sflash.c */ @@ -84,9 +87,26 @@ extern void __exit bcma_host_pci_exit(void); /* driver_pci.c */ u32 bcma_pcie_read(struct bcma_drv_pci *pc, u32 address); +extern int bcma_chipco_watchdog_register(struct bcma_drv_cc *cc); + #ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE -bool __devinit bcma_core_pci_is_in_hostmode(struct bcma_drv_pci *pc); -void __devinit bcma_core_pci_hostmode_init(struct bcma_drv_pci *pc); +bool bcma_core_pci_is_in_hostmode(struct bcma_drv_pci *pc); +void bcma_core_pci_hostmode_init(struct bcma_drv_pci *pc); #endif /* CONFIG_BCMA_DRIVER_PCI_HOSTMODE */ +#ifdef CONFIG_BCMA_DRIVER_GPIO +/* driver_gpio.c */ +int bcma_gpio_init(struct bcma_drv_cc *cc); +int bcma_gpio_unregister(struct bcma_drv_cc *cc); +#else +static inline int bcma_gpio_init(struct bcma_drv_cc *cc) +{ + return -ENOTSUPP; +} +static inline int bcma_gpio_unregister(struct bcma_drv_cc *cc) +{ + return 0; +} +#endif /* CONFIG_BCMA_DRIVER_GPIO */ + #endif diff --git a/drivers/bcma/driver_chipcommon.c b/drivers/bcma/driver_chipcommon.c index a4c3ebcc4c86..28fa50ad87be 100644 --- a/drivers/bcma/driver_chipcommon.c +++ b/drivers/bcma/driver_chipcommon.c @@ -4,12 +4,15 @@ * * Copyright 2005, Broadcom Corporation * Copyright 2006, 2007, Michael Buesch <m@bues.ch> + * Copyright 2012, Hauke Mehrtens <hauke@hauke-m.de> * * Licensed under the GNU/GPL. See COPYING for details. */ #include "bcma_private.h" +#include <linux/bcm47xx_wdt.h> #include <linux/export.h> +#include <linux/platform_device.h> #include <linux/bcma/bcma.h> static inline u32 bcma_cc_write32_masked(struct bcma_drv_cc *cc, u16 offset, @@ -22,20 +25,119 @@ static inline u32 bcma_cc_write32_masked(struct bcma_drv_cc *cc, u16 offset, return value; } -void bcma_core_chipcommon_init(struct bcma_drv_cc *cc) +static u32 bcma_chipco_get_alp_clock(struct bcma_drv_cc *cc) { - u32 leddc_on = 10; - u32 leddc_off = 90; + if (cc->capabilities & BCMA_CC_CAP_PMU) + return bcma_pmu_get_alp_clock(cc); - if (cc->setup_done) + return 20000000; +} + +static u32 bcma_chipco_watchdog_get_max_timer(struct bcma_drv_cc *cc) +{ + struct bcma_bus *bus = cc->core->bus; + u32 nb; + + if (cc->capabilities & BCMA_CC_CAP_PMU) { + if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706) + nb = 32; + else if (cc->core->id.rev < 26) + nb = 16; + else + nb = (cc->core->id.rev >= 37) ? 32 : 24; + } else { + nb = 28; + } + if (nb == 32) + return 0xffffffff; + else + return (1 << nb) - 1; +} + +static u32 bcma_chipco_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt, + u32 ticks) +{ + struct bcma_drv_cc *cc = bcm47xx_wdt_get_drvdata(wdt); + + return bcma_chipco_watchdog_timer_set(cc, ticks); +} + +static u32 bcma_chipco_watchdog_timer_set_ms_wdt(struct bcm47xx_wdt *wdt, + u32 ms) +{ + struct bcma_drv_cc *cc = bcm47xx_wdt_get_drvdata(wdt); + u32 ticks; + + ticks = bcma_chipco_watchdog_timer_set(cc, cc->ticks_per_ms * ms); + return ticks / cc->ticks_per_ms; +} + +static int bcma_chipco_watchdog_ticks_per_ms(struct bcma_drv_cc *cc) +{ + struct bcma_bus *bus = cc->core->bus; + + if (cc->capabilities & BCMA_CC_CAP_PMU) { + if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706) + /* 4706 CC and PMU watchdogs are clocked at 1/4 of ALP clock */ + return bcma_chipco_get_alp_clock(cc) / 4000; + else + /* based on 32KHz ILP clock */ + return 32; + } else { + return bcma_chipco_get_alp_clock(cc) / 1000; + } +} + +int bcma_chipco_watchdog_register(struct bcma_drv_cc *cc) +{ + struct bcm47xx_wdt wdt = {}; + struct platform_device *pdev; + + wdt.driver_data = cc; + wdt.timer_set = bcma_chipco_watchdog_timer_set_wdt; + wdt.timer_set_ms = bcma_chipco_watchdog_timer_set_ms_wdt; + wdt.max_timer_ms = bcma_chipco_watchdog_get_max_timer(cc) / cc->ticks_per_ms; + + pdev = platform_device_register_data(NULL, "bcm47xx-wdt", + cc->core->bus->num, &wdt, + sizeof(wdt)); + if (IS_ERR(pdev)) + return PTR_ERR(pdev); + + cc->watchdog = pdev; + + return 0; +} + +void bcma_core_chipcommon_early_init(struct bcma_drv_cc *cc) +{ + if (cc->early_setup_done) return; + spin_lock_init(&cc->gpio_lock); + if (cc->core->id.rev >= 11) cc->status = bcma_cc_read32(cc, BCMA_CC_CHIPSTAT); cc->capabilities = bcma_cc_read32(cc, BCMA_CC_CAP); if (cc->core->id.rev >= 35) cc->capabilities_ext = bcma_cc_read32(cc, BCMA_CC_CAP_EXT); + if (cc->capabilities & BCMA_CC_CAP_PMU) + bcma_pmu_early_init(cc); + + cc->early_setup_done = true; +} + +void bcma_core_chipcommon_init(struct bcma_drv_cc *cc) +{ + u32 leddc_on = 10; + u32 leddc_off = 90; + + if (cc->setup_done) + return; + + bcma_core_chipcommon_early_init(cc); + if (cc->core->id.rev >= 20) { bcma_cc_write32(cc, BCMA_CC_GPIOPULLUP, 0); bcma_cc_write32(cc, BCMA_CC_GPIOPULLDOWN, 0); @@ -56,15 +158,33 @@ void bcma_core_chipcommon_init(struct bcma_drv_cc *cc) ((leddc_on << BCMA_CC_GPIOTIMER_ONTIME_SHIFT) | (leddc_off << BCMA_CC_GPIOTIMER_OFFTIME_SHIFT))); } + cc->ticks_per_ms = bcma_chipco_watchdog_ticks_per_ms(cc); cc->setup_done = true; } /* Set chip watchdog reset timer to fire in 'ticks' backplane cycles */ -void bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks) +u32 bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks) { - /* instant NMI */ - bcma_cc_write32(cc, BCMA_CC_WATCHDOG, ticks); + u32 maxt; + enum bcma_clkmode clkmode; + + maxt = bcma_chipco_watchdog_get_max_timer(cc); + if (cc->capabilities & BCMA_CC_CAP_PMU) { + if (ticks == 1) + ticks = 2; + else if (ticks > maxt) + ticks = maxt; + bcma_cc_write32(cc, BCMA_CC_PMU_WATCHDOG, ticks); + } else { + clkmode = ticks ? BCMA_CLKMODE_FAST : BCMA_CLKMODE_DYNAMIC; + bcma_core_set_clockmode(cc->core, clkmode); + if (ticks > maxt) + ticks = maxt; + /* instant NMI */ + bcma_cc_write32(cc, BCMA_CC_WATCHDOG, ticks); + } + return ticks; } void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value) @@ -84,28 +204,97 @@ u32 bcma_chipco_gpio_in(struct bcma_drv_cc *cc, u32 mask) u32 bcma_chipco_gpio_out(struct bcma_drv_cc *cc, u32 mask, u32 value) { - return bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUT, mask, value); + unsigned long flags; + u32 res; + + spin_lock_irqsave(&cc->gpio_lock, flags); + res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUT, mask, value); + spin_unlock_irqrestore(&cc->gpio_lock, flags); + + return res; } u32 bcma_chipco_gpio_outen(struct bcma_drv_cc *cc, u32 mask, u32 value) { - return bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUTEN, mask, value); + unsigned long flags; + u32 res; + + spin_lock_irqsave(&cc->gpio_lock, flags); + res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUTEN, mask, value); + spin_unlock_irqrestore(&cc->gpio_lock, flags); + + return res; } +/* + * If the bit is set to 0, chipcommon controlls this GPIO, + * if the bit is set to 1, it is used by some part of the chip and not our code. + */ u32 bcma_chipco_gpio_control(struct bcma_drv_cc *cc, u32 mask, u32 value) { - return bcma_cc_write32_masked(cc, BCMA_CC_GPIOCTL, mask, value); + unsigned long flags; + u32 res; + + spin_lock_irqsave(&cc->gpio_lock, flags); + res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOCTL, mask, value); + spin_unlock_irqrestore(&cc->gpio_lock, flags); + + return res; } EXPORT_SYMBOL_GPL(bcma_chipco_gpio_control); u32 bcma_chipco_gpio_intmask(struct bcma_drv_cc *cc, u32 mask, u32 value) { - return bcma_cc_write32_masked(cc, BCMA_CC_GPIOIRQ, mask, value); + unsigned long flags; + u32 res; + + spin_lock_irqsave(&cc->gpio_lock, flags); + res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOIRQ, mask, value); + spin_unlock_irqrestore(&cc->gpio_lock, flags); + + return res; } u32 bcma_chipco_gpio_polarity(struct bcma_drv_cc *cc, u32 mask, u32 value) { - return bcma_cc_write32_masked(cc, BCMA_CC_GPIOPOL, mask, value); + unsigned long flags; + u32 res; + + spin_lock_irqsave(&cc->gpio_lock, flags); + res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOPOL, mask, value); + spin_unlock_irqrestore(&cc->gpio_lock, flags); + + return res; +} + +u32 bcma_chipco_gpio_pullup(struct bcma_drv_cc *cc, u32 mask, u32 value) +{ + unsigned long flags; + u32 res; + + if (cc->core->id.rev < 20) + return 0; + + spin_lock_irqsave(&cc->gpio_lock, flags); + res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOPULLUP, mask, value); + spin_unlock_irqrestore(&cc->gpio_lock, flags); + + return res; +} + +u32 bcma_chipco_gpio_pulldown(struct bcma_drv_cc *cc, u32 mask, u32 value) +{ + unsigned long flags; + u32 res; + + if (cc->core->id.rev < 20) + return 0; + + spin_lock_irqsave(&cc->gpio_lock, flags); + res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOPULLDOWN, mask, value); + spin_unlock_irqrestore(&cc->gpio_lock, flags); + + return res; } #ifdef CONFIG_BCMA_DRIVER_MIPS @@ -118,8 +307,7 @@ void bcma_chipco_serial_init(struct bcma_drv_cc *cc) struct bcma_serial_port *ports = cc->serial_ports; if (ccrev >= 11 && ccrev != 15) { - /* Fixed ALP clock */ - baud_base = bcma_pmu_alp_clock(cc); + baud_base = bcma_chipco_get_alp_clock(cc); if (ccrev >= 21) { /* Turn off UART clock before switching clocksource. */ bcma_cc_write32(cc, BCMA_CC_CORECTL, @@ -141,7 +329,7 @@ void bcma_chipco_serial_init(struct bcma_drv_cc *cc) return; } - irq = bcma_core_mips_irq(cc->core); + irq = bcma_core_irq(cc->core); /* Determine the registers of the UARTs */ cc->nr_serial_ports = (cc->capabilities & BCMA_CC_CAP_NRUART); diff --git a/drivers/bcma/driver_chipcommon_nflash.c b/drivers/bcma/driver_chipcommon_nflash.c index 9042781edec3..d4f699aef8c4 100644 --- a/drivers/bcma/driver_chipcommon_nflash.c +++ b/drivers/bcma/driver_chipcommon_nflash.c @@ -5,11 +5,11 @@ * Licensed under the GNU/GPL. See COPYING for details. */ +#include "bcma_private.h" + #include <linux/platform_device.h> #include <linux/bcma/bcma.h> -#include "bcma_private.h" - struct platform_device bcma_nflash_dev = { .name = "bcma_nflash", .num_resources = 0, @@ -21,7 +21,7 @@ int bcma_nflash_init(struct bcma_drv_cc *cc) struct bcma_bus *bus = cc->core->bus; if (bus->chipinfo.id != BCMA_CHIP_ID_BCM4706 && - cc->core->id.rev != 0x38) { + cc->core->id.rev != 38) { bcma_err(bus, "NAND flash on unsupported board!\n"); return -ENOTSUPP; } @@ -32,6 +32,9 @@ int bcma_nflash_init(struct bcma_drv_cc *cc) } cc->nflash.present = true; + if (cc->core->id.rev == 38 && + (cc->status & BCMA_CC_CHIPST_5357_NAND_BOOT)) + cc->nflash.boot = true; /* Prepare platform device, but don't register it yet. It's too early, * malloc (required by device_private_init) is not available yet. */ diff --git a/drivers/bcma/driver_chipcommon_pmu.c b/drivers/bcma/driver_chipcommon_pmu.c index 201faf106b3f..932b101dee36 100644 --- a/drivers/bcma/driver_chipcommon_pmu.c +++ b/drivers/bcma/driver_chipcommon_pmu.c @@ -13,12 +13,13 @@ #include <linux/export.h> #include <linux/bcma/bcma.h> -static u32 bcma_chipco_pll_read(struct bcma_drv_cc *cc, u32 offset) +u32 bcma_chipco_pll_read(struct bcma_drv_cc *cc, u32 offset) { bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset); bcma_cc_read32(cc, BCMA_CC_PLLCTL_ADDR); return bcma_cc_read32(cc, BCMA_CC_PLLCTL_DATA); } +EXPORT_SYMBOL_GPL(bcma_chipco_pll_read); void bcma_chipco_pll_write(struct bcma_drv_cc *cc, u32 offset, u32 value) { @@ -144,7 +145,7 @@ static void bcma_pmu_workarounds(struct bcma_drv_cc *cc) } } -void bcma_pmu_init(struct bcma_drv_cc *cc) +void bcma_pmu_early_init(struct bcma_drv_cc *cc) { u32 pmucap; @@ -153,7 +154,10 @@ void bcma_pmu_init(struct bcma_drv_cc *cc) bcma_debug(cc->core->bus, "Found rev %u PMU (capabilities 0x%08X)\n", cc->pmu.rev, pmucap); +} +void bcma_pmu_init(struct bcma_drv_cc *cc) +{ if (cc->pmu.rev == 1) bcma_cc_mask32(cc, BCMA_CC_PMU_CTL, ~BCMA_CC_PMU_CTL_NOILPONW); @@ -165,7 +169,7 @@ void bcma_pmu_init(struct bcma_drv_cc *cc) bcma_pmu_workarounds(cc); } -u32 bcma_pmu_alp_clock(struct bcma_drv_cc *cc) +u32 bcma_pmu_get_alp_clock(struct bcma_drv_cc *cc) { struct bcma_bus *bus = cc->core->bus; @@ -193,7 +197,7 @@ u32 bcma_pmu_alp_clock(struct bcma_drv_cc *cc) /* Find the output of the "m" pll divider given pll controls that start with * pllreg "pll0" i.e. 12 for main 6 for phy, 0 for misc. */ -static u32 bcma_pmu_clock(struct bcma_drv_cc *cc, u32 pll0, u32 m) +static u32 bcma_pmu_pll_clock(struct bcma_drv_cc *cc, u32 pll0, u32 m) { u32 tmp, div, ndiv, p1, p2, fc; struct bcma_bus *bus = cc->core->bus; @@ -222,14 +226,14 @@ static u32 bcma_pmu_clock(struct bcma_drv_cc *cc, u32 pll0, u32 m) ndiv = (tmp & BCMA_CC_PPL_NDIV_MASK) >> BCMA_CC_PPL_NDIV_SHIFT; /* Do calculation in Mhz */ - fc = bcma_pmu_alp_clock(cc) / 1000000; + fc = bcma_pmu_get_alp_clock(cc) / 1000000; fc = (p1 * ndiv * fc) / p2; /* Return clock in Hertz */ return (fc / div) * 1000000; } -static u32 bcma_pmu_clock_bcm4706(struct bcma_drv_cc *cc, u32 pll0, u32 m) +static u32 bcma_pmu_pll_clock_bcm4706(struct bcma_drv_cc *cc, u32 pll0, u32 m) { u32 tmp, ndiv, p1div, p2div; u32 clock; @@ -260,7 +264,7 @@ static u32 bcma_pmu_clock_bcm4706(struct bcma_drv_cc *cc, u32 pll0, u32 m) } /* query bus clock frequency for PMU-enabled chipcommon */ -static u32 bcma_pmu_get_clockcontrol(struct bcma_drv_cc *cc) +u32 bcma_pmu_get_bus_clock(struct bcma_drv_cc *cc) { struct bcma_bus *bus = cc->core->bus; @@ -268,40 +272,43 @@ static u32 bcma_pmu_get_clockcontrol(struct bcma_drv_cc *cc) case BCMA_CHIP_ID_BCM4716: case BCMA_CHIP_ID_BCM4748: case BCMA_CHIP_ID_BCM47162: - return bcma_pmu_clock(cc, BCMA_CC_PMU4716_MAINPLL_PLL0, - BCMA_CC_PMU5_MAINPLL_SSB); + return bcma_pmu_pll_clock(cc, BCMA_CC_PMU4716_MAINPLL_PLL0, + BCMA_CC_PMU5_MAINPLL_SSB); case BCMA_CHIP_ID_BCM5356: - return bcma_pmu_clock(cc, BCMA_CC_PMU5356_MAINPLL_PLL0, - BCMA_CC_PMU5_MAINPLL_SSB); + return bcma_pmu_pll_clock(cc, BCMA_CC_PMU5356_MAINPLL_PLL0, + BCMA_CC_PMU5_MAINPLL_SSB); case BCMA_CHIP_ID_BCM5357: case BCMA_CHIP_ID_BCM4749: - return bcma_pmu_clock(cc, BCMA_CC_PMU5357_MAINPLL_PLL0, - BCMA_CC_PMU5_MAINPLL_SSB); + return bcma_pmu_pll_clock(cc, BCMA_CC_PMU5357_MAINPLL_PLL0, + BCMA_CC_PMU5_MAINPLL_SSB); case BCMA_CHIP_ID_BCM4706: - return bcma_pmu_clock_bcm4706(cc, BCMA_CC_PMU4706_MAINPLL_PLL0, - BCMA_CC_PMU5_MAINPLL_SSB); + return bcma_pmu_pll_clock_bcm4706(cc, + BCMA_CC_PMU4706_MAINPLL_PLL0, + BCMA_CC_PMU5_MAINPLL_SSB); case BCMA_CHIP_ID_BCM53572: return 75000000; default: - bcma_warn(bus, "No backplane clock specified for %04X device, pmu rev. %d, using default %d Hz\n", + bcma_warn(bus, "No bus clock specified for %04X device, pmu rev. %d, using default %d Hz\n", bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_HT_CLOCK); } return BCMA_CC_PMU_HT_CLOCK; } +EXPORT_SYMBOL_GPL(bcma_pmu_get_bus_clock); /* query cpu clock frequency for PMU-enabled chipcommon */ -u32 bcma_pmu_get_clockcpu(struct bcma_drv_cc *cc) +u32 bcma_pmu_get_cpu_clock(struct bcma_drv_cc *cc) { struct bcma_bus *bus = cc->core->bus; if (bus->chipinfo.id == BCMA_CHIP_ID_BCM53572) return 300000000; + /* New PMUs can have different clock for bus and CPU */ if (cc->pmu.rev >= 5) { u32 pll; switch (bus->chipinfo.id) { case BCMA_CHIP_ID_BCM4706: - return bcma_pmu_clock_bcm4706(cc, + return bcma_pmu_pll_clock_bcm4706(cc, BCMA_CC_PMU4706_MAINPLL_PLL0, BCMA_CC_PMU5_MAINPLL_CPU); case BCMA_CHIP_ID_BCM5356: @@ -316,10 +323,11 @@ u32 bcma_pmu_get_clockcpu(struct bcma_drv_cc *cc) break; } - return bcma_pmu_clock(cc, pll, BCMA_CC_PMU5_MAINPLL_CPU); + return bcma_pmu_pll_clock(cc, pll, BCMA_CC_PMU5_MAINPLL_CPU); } - return bcma_pmu_get_clockcontrol(cc); + /* On old PMUs CPU has the same clock as the bus */ + return bcma_pmu_get_bus_clock(cc); } static void bcma_pmu_spuravoid_pll_write(struct bcma_drv_cc *cc, u32 offset, diff --git a/drivers/bcma/driver_chipcommon_sflash.c b/drivers/bcma/driver_chipcommon_sflash.c index 2c4eec2ca5a0..e6ed4fe5dced 100644 --- a/drivers/bcma/driver_chipcommon_sflash.c +++ b/drivers/bcma/driver_chipcommon_sflash.c @@ -5,14 +5,14 @@ * Licensed under the GNU/GPL. See COPYING for details. */ +#include "bcma_private.h" + #include <linux/platform_device.h> #include <linux/bcma/bcma.h> -#include "bcma_private.h" - static struct resource bcma_sflash_resource = { .name = "bcma_sflash", - .start = BCMA_SFLASH, + .start = BCMA_SOC_FLASH2, .end = 0, .flags = IORESOURCE_MEM | IORESOURCE_READONLY, }; @@ -31,15 +31,42 @@ struct bcma_sflash_tbl_e { }; static struct bcma_sflash_tbl_e bcma_sflash_st_tbl[] = { - { "", 0x14, 0x10000, 32, }, + { "M25P20", 0x11, 0x10000, 4, }, + { "M25P40", 0x12, 0x10000, 8, }, + + { "M25P16", 0x14, 0x10000, 32, }, + { "M25P32", 0x15, 0x10000, 64, }, + { "M25P64", 0x16, 0x10000, 128, }, + { "M25FL128", 0x17, 0x10000, 256, }, { 0 }, }; static struct bcma_sflash_tbl_e bcma_sflash_sst_tbl[] = { + { "SST25WF512", 1, 0x1000, 16, }, + { "SST25VF512", 0x48, 0x1000, 16, }, + { "SST25WF010", 2, 0x1000, 32, }, + { "SST25VF010", 0x49, 0x1000, 32, }, + { "SST25WF020", 3, 0x1000, 64, }, + { "SST25VF020", 0x43, 0x1000, 64, }, + { "SST25WF040", 4, 0x1000, 128, }, + { "SST25VF040", 0x44, 0x1000, 128, }, + { "SST25VF040B", 0x8d, 0x1000, 128, }, + { "SST25WF080", 5, 0x1000, 256, }, + { "SST25VF080B", 0x8e, 0x1000, 256, }, + { "SST25VF016", 0x41, 0x1000, 512, }, + { "SST25VF032", 0x4a, 0x1000, 1024, }, + { "SST25VF064", 0x4b, 0x1000, 2048, }, { 0 }, }; static struct bcma_sflash_tbl_e bcma_sflash_at_tbl[] = { + { "AT45DB011", 0xc, 256, 512, }, + { "AT45DB021", 0x14, 256, 1024, }, + { "AT45DB041", 0x1c, 256, 2048, }, + { "AT45DB081", 0x24, 256, 4096, }, + { "AT45DB161", 0x2c, 512, 4096, }, + { "AT45DB321", 0x34, 512, 8192, }, + { "AT45DB642", 0x3c, 1024, 8192, }, { 0 }, }; @@ -84,6 +111,8 @@ int bcma_sflash_init(struct bcma_drv_cc *cc) break; } break; + case 0x13: + return -ENOTSUPP; default: for (e = bcma_sflash_st_tbl; e->name; e++) { if (e->id == id) @@ -116,7 +145,7 @@ int bcma_sflash_init(struct bcma_drv_cc *cc) return -ENOTSUPP; } - sflash->window = BCMA_SFLASH; + sflash->window = BCMA_SOC_FLASH2; sflash->blocksize = e->blocksize; sflash->numblocks = e->numblocks; sflash->size = sflash->blocksize * sflash->numblocks; diff --git a/drivers/bcma/driver_gmac_cmn.c b/drivers/bcma/driver_gmac_cmn.c index 834225f65e8f..dcb137926d31 100644 --- a/drivers/bcma/driver_gmac_cmn.c +++ b/drivers/bcma/driver_gmac_cmn.c @@ -8,7 +8,7 @@ #include "bcma_private.h" #include <linux/bcma/bcma.h> -void __devinit bcma_core_gmac_cmn_init(struct bcma_drv_gmac_cmn *gc) +void bcma_core_gmac_cmn_init(struct bcma_drv_gmac_cmn *gc) { mutex_init(&gc->phy_mutex); } diff --git a/drivers/bcma/driver_gpio.c b/drivers/bcma/driver_gpio.c new file mode 100644 index 000000000000..45f0996a3752 --- /dev/null +++ b/drivers/bcma/driver_gpio.c @@ -0,0 +1,114 @@ +/* + * Broadcom specific AMBA + * GPIO driver + * + * Copyright 2011, Broadcom Corporation + * Copyright 2012, Hauke Mehrtens <hauke@hauke-m.de> + * + * Licensed under the GNU/GPL. See COPYING for details. + */ + +#include <linux/gpio.h> +#include <linux/export.h> +#include <linux/bcma/bcma.h> + +#include "bcma_private.h" + +static inline struct bcma_drv_cc *bcma_gpio_get_cc(struct gpio_chip *chip) +{ + return container_of(chip, struct bcma_drv_cc, gpio); +} + +static int bcma_gpio_get_value(struct gpio_chip *chip, unsigned gpio) +{ + struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip); + + return !!bcma_chipco_gpio_in(cc, 1 << gpio); +} + +static void bcma_gpio_set_value(struct gpio_chip *chip, unsigned gpio, + int value) +{ + struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip); + + bcma_chipco_gpio_out(cc, 1 << gpio, value ? 1 << gpio : 0); +} + +static int bcma_gpio_direction_input(struct gpio_chip *chip, unsigned gpio) +{ + struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip); + + bcma_chipco_gpio_outen(cc, 1 << gpio, 0); + return 0; +} + +static int bcma_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, + int value) +{ + struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip); + + bcma_chipco_gpio_outen(cc, 1 << gpio, 1 << gpio); + bcma_chipco_gpio_out(cc, 1 << gpio, value ? 1 << gpio : 0); + return 0; +} + +static int bcma_gpio_request(struct gpio_chip *chip, unsigned gpio) +{ + struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip); + + bcma_chipco_gpio_control(cc, 1 << gpio, 0); + /* clear pulldown */ + bcma_chipco_gpio_pulldown(cc, 1 << gpio, 0); + /* Set pullup */ + bcma_chipco_gpio_pullup(cc, 1 << gpio, 1 << gpio); + + return 0; +} + +static void bcma_gpio_free(struct gpio_chip *chip, unsigned gpio) +{ + struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip); + + /* clear pullup */ + bcma_chipco_gpio_pullup(cc, 1 << gpio, 0); +} + +static int bcma_gpio_to_irq(struct gpio_chip *chip, unsigned gpio) +{ + struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip); + + if (cc->core->bus->hosttype == BCMA_HOSTTYPE_SOC) + return bcma_core_irq(cc->core); + else + return -EINVAL; +} + +int bcma_gpio_init(struct bcma_drv_cc *cc) +{ + struct gpio_chip *chip = &cc->gpio; + + chip->label = "bcma_gpio"; + chip->owner = THIS_MODULE; + chip->request = bcma_gpio_request; + chip->free = bcma_gpio_free; + chip->get = bcma_gpio_get_value; + chip->set = bcma_gpio_set_value; + chip->direction_input = bcma_gpio_direction_input; + chip->direction_output = bcma_gpio_direction_output; + chip->to_irq = bcma_gpio_to_irq; + chip->ngpio = 16; + /* There is just one SoC in one device and its GPIO addresses should be + * deterministic to address them more easily. The other buses could get + * a random base number. */ + if (cc->core->bus->hosttype == BCMA_HOSTTYPE_SOC) + chip->base = 0; + else + chip->base = -1; + + return gpiochip_add(chip); +} + +int bcma_gpio_unregister(struct bcma_drv_cc *cc) +{ + return gpiochip_remove(&cc->gpio); +} diff --git a/drivers/bcma/driver_mips.c b/drivers/bcma/driver_mips.c index cc65b45b4368..9a7f0e3ab5a3 100644 --- a/drivers/bcma/driver_mips.c +++ b/drivers/bcma/driver_mips.c @@ -14,11 +14,33 @@ #include <linux/bcma/bcma.h> +#include <linux/mtd/physmap.h> +#include <linux/platform_device.h> #include <linux/serial.h> #include <linux/serial_core.h> #include <linux/serial_reg.h> #include <linux/time.h> +static const char *part_probes[] = { "bcm47xxpart", NULL }; + +static struct physmap_flash_data bcma_pflash_data = { + .part_probe_types = part_probes, +}; + +static struct resource bcma_pflash_resource = { + .name = "bcma_pflash", + .flags = IORESOURCE_MEM, +}; + +struct platform_device bcma_pflash_dev = { + .name = "physmap-flash", + .dev = { + .platform_data = &bcma_pflash_data, + }, + .resource = &bcma_pflash_resource, + .num_resources = 1, +}; + /* The 47162a0 hangs when reading MIPS DMP registers registers */ static inline bool bcma_core_mips_bcm47162a0_quirk(struct bcma_device *dev) { @@ -74,28 +96,41 @@ static u32 bcma_core_mips_irqflag(struct bcma_device *dev) return dev->core_index; flag = bcma_aread32(dev, BCMA_MIPS_OOBSELOUTA30); - return flag & 0x1F; + if (flag) + return flag & 0x1F; + else + return 0x3f; } /* Get the MIPS IRQ assignment for a specified device. * If unassigned, 0 is returned. + * If disabled, 5 is returned. + * If not supported, 6 is returned. */ -unsigned int bcma_core_mips_irq(struct bcma_device *dev) +static unsigned int bcma_core_mips_irq(struct bcma_device *dev) { struct bcma_device *mdev = dev->bus->drv_mips.core; u32 irqflag; unsigned int irq; irqflag = bcma_core_mips_irqflag(dev); + if (irqflag == 0x3f) + return 6; - for (irq = 1; irq <= 4; irq++) + for (irq = 0; irq <= 4; irq++) if (bcma_read32(mdev, BCMA_MIPS_MIPS74K_INTMASK(irq)) & (1 << irqflag)) return irq; - return 0; + return 5; } -EXPORT_SYMBOL(bcma_core_mips_irq); + +unsigned int bcma_core_irq(struct bcma_device *dev) +{ + unsigned int mips_irq = bcma_core_mips_irq(dev); + return mips_irq <= 4 ? mips_irq + 2 : 0; +} +EXPORT_SYMBOL(bcma_core_irq); static void bcma_core_mips_set_irq(struct bcma_device *dev, unsigned int irq) { @@ -114,8 +149,8 @@ static void bcma_core_mips_set_irq(struct bcma_device *dev, unsigned int irq) bcma_write32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0), bcma_read32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0)) & ~(1 << irqflag)); - else - bcma_write32(mdev, BCMA_MIPS_MIPS74K_INTMASK(irq), 0); + else if (oldirq != 5) + bcma_write32(mdev, BCMA_MIPS_MIPS74K_INTMASK(oldirq), 0); /* assign the new one */ if (irq == 0) { @@ -123,9 +158,9 @@ static void bcma_core_mips_set_irq(struct bcma_device *dev, unsigned int irq) bcma_read32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0)) | (1 << irqflag)); } else { - u32 oldirqflag = bcma_read32(mdev, - BCMA_MIPS_MIPS74K_INTMASK(irq)); - if (oldirqflag) { + u32 irqinitmask = bcma_read32(mdev, + BCMA_MIPS_MIPS74K_INTMASK(irq)); + if (irqinitmask) { struct bcma_device *core; /* backplane irq line is in use, find out who uses @@ -133,7 +168,7 @@ static void bcma_core_mips_set_irq(struct bcma_device *dev, unsigned int irq) */ list_for_each_entry(core, &bus->cores, list) { if ((1 << bcma_core_mips_irqflag(core)) == - oldirqflag) { + irqinitmask) { bcma_core_mips_set_irq(core, 0); break; } @@ -143,15 +178,31 @@ static void bcma_core_mips_set_irq(struct bcma_device *dev, unsigned int irq) 1 << irqflag); } - bcma_info(bus, "set_irq: core 0x%04x, irq %d => %d\n", - dev->id.id, oldirq + 2, irq + 2); + bcma_debug(bus, "set_irq: core 0x%04x, irq %d => %d\n", + dev->id.id, oldirq <= 4 ? oldirq + 2 : 0, irq + 2); +} + +static void bcma_core_mips_set_irq_name(struct bcma_bus *bus, unsigned int irq, + u16 coreid, u8 unit) +{ + struct bcma_device *core; + + core = bcma_find_core_unit(bus, coreid, unit); + if (!core) { + bcma_warn(bus, + "Can not find core (id: 0x%x, unit %i) for IRQ configuration.\n", + coreid, unit); + return; + } + + bcma_core_mips_set_irq(core, irq); } static void bcma_core_mips_print_irq(struct bcma_device *dev, unsigned int irq) { int i; static const char *irq_name[] = {"2(S)", "3", "4", "5", "6", "D", "I"}; - printk(KERN_INFO KBUILD_MODNAME ": core 0x%04x, irq :", dev->id.id); + printk(KERN_DEBUG KBUILD_MODNAME ": core 0x%04x, irq :", dev->id.id); for (i = 0; i <= 6; i++) printk(" %s%s", irq_name[i], i == irq ? "*" : " "); printk("\n"); @@ -171,7 +222,7 @@ u32 bcma_cpu_clock(struct bcma_drv_mips *mcore) struct bcma_bus *bus = mcore->core->bus; if (bus->drv_cc.capabilities & BCMA_CC_CAP_PMU) - return bcma_pmu_get_clockcpu(&bus->drv_cc); + return bcma_pmu_get_cpu_clock(&bus->drv_cc); bcma_err(bus, "No PMU available, need this to get the cpu clock\n"); return 0; @@ -181,85 +232,143 @@ EXPORT_SYMBOL(bcma_cpu_clock); static void bcma_core_mips_flash_detect(struct bcma_drv_mips *mcore) { struct bcma_bus *bus = mcore->core->bus; + struct bcma_drv_cc *cc = &bus->drv_cc; + struct bcma_pflash *pflash = &cc->pflash; - switch (bus->drv_cc.capabilities & BCMA_CC_CAP_FLASHT) { + switch (cc->capabilities & BCMA_CC_CAP_FLASHT) { case BCMA_CC_FLASHT_STSER: case BCMA_CC_FLASHT_ATSER: bcma_debug(bus, "Found serial flash\n"); - bcma_sflash_init(&bus->drv_cc); + bcma_sflash_init(cc); break; case BCMA_CC_FLASHT_PARA: bcma_debug(bus, "Found parallel flash\n"); - bus->drv_cc.pflash.window = 0x1c000000; - bus->drv_cc.pflash.window_size = 0x02000000; + pflash->present = true; + pflash->window = BCMA_SOC_FLASH2; + pflash->window_size = BCMA_SOC_FLASH2_SZ; - if ((bcma_read32(bus->drv_cc.core, BCMA_CC_FLASH_CFG) & + if ((bcma_read32(cc->core, BCMA_CC_FLASH_CFG) & BCMA_CC_FLASH_CFG_DS) == 0) - bus->drv_cc.pflash.buswidth = 1; + pflash->buswidth = 1; else - bus->drv_cc.pflash.buswidth = 2; + pflash->buswidth = 2; + + bcma_pflash_data.width = pflash->buswidth; + bcma_pflash_resource.start = pflash->window; + bcma_pflash_resource.end = pflash->window + pflash->window_size; + break; default: bcma_err(bus, "Flash type not supported\n"); } - if (bus->drv_cc.core->id.rev == 38 || + if (cc->core->id.rev == 38 || bus->chipinfo.id == BCMA_CHIP_ID_BCM4706) { - if (bus->drv_cc.capabilities & BCMA_CC_CAP_NFLASH) { + if (cc->capabilities & BCMA_CC_CAP_NFLASH) { bcma_debug(bus, "Found NAND flash\n"); - bcma_nflash_init(&bus->drv_cc); + bcma_nflash_init(cc); } } } +void bcma_core_mips_early_init(struct bcma_drv_mips *mcore) +{ + struct bcma_bus *bus = mcore->core->bus; + + if (mcore->early_setup_done) + return; + + bcma_chipco_serial_init(&bus->drv_cc); + bcma_core_mips_flash_detect(mcore); + + mcore->early_setup_done = true; +} + +static void bcma_fix_i2s_irqflag(struct bcma_bus *bus) +{ + struct bcma_device *cpu, *pcie, *i2s; + + /* Fixup the interrupts in 4716/4748 for i2s core (2010 Broadcom SDK) + * (IRQ flags > 7 are ignored when setting the interrupt masks) + */ + if (bus->chipinfo.id != BCMA_CHIP_ID_BCM4716 && + bus->chipinfo.id != BCMA_CHIP_ID_BCM4748) + return; + + cpu = bcma_find_core(bus, BCMA_CORE_MIPS_74K); + pcie = bcma_find_core(bus, BCMA_CORE_PCIE); + i2s = bcma_find_core(bus, BCMA_CORE_I2S); + if (cpu && pcie && i2s && + bcma_aread32(cpu, BCMA_MIPS_OOBSELINA74) == 0x08060504 && + bcma_aread32(pcie, BCMA_MIPS_OOBSELINA74) == 0x08060504 && + bcma_aread32(i2s, BCMA_MIPS_OOBSELOUTA30) == 0x88) { + bcma_awrite32(cpu, BCMA_MIPS_OOBSELINA74, 0x07060504); + bcma_awrite32(pcie, BCMA_MIPS_OOBSELINA74, 0x07060504); + bcma_awrite32(i2s, BCMA_MIPS_OOBSELOUTA30, 0x87); + bcma_debug(bus, + "Moved i2s interrupt to oob line 7 instead of 8\n"); + } +} + void bcma_core_mips_init(struct bcma_drv_mips *mcore) { struct bcma_bus *bus; struct bcma_device *core; bus = mcore->core->bus; - bcma_info(bus, "Initializing MIPS core...\n"); + if (mcore->setup_done) + return; + + bcma_debug(bus, "Initializing MIPS core...\n"); - if (!mcore->setup_done) - mcore->assigned_irqs = 1; + bcma_core_mips_early_init(mcore); - /* Assign IRQs to all cores on the bus */ - list_for_each_entry(core, &bus->cores, list) { - int mips_irq; - if (core->irq) - continue; + bcma_fix_i2s_irqflag(bus); - mips_irq = bcma_core_mips_irq(core); - if (mips_irq > 4) - core->irq = 0; - else - core->irq = mips_irq + 2; - if (core->irq > 5) - continue; - switch (core->id.id) { - case BCMA_CORE_PCI: - case BCMA_CORE_PCIE: - case BCMA_CORE_ETHERNET: - case BCMA_CORE_ETHERNET_GBIT: - case BCMA_CORE_MAC_GBIT: - case BCMA_CORE_80211: - case BCMA_CORE_USB20_HOST: - /* These devices get their own IRQ line if available, - * the rest goes on IRQ0 - */ - if (mcore->assigned_irqs <= 4) - bcma_core_mips_set_irq(core, - mcore->assigned_irqs++); - break; + switch (bus->chipinfo.id) { + case BCMA_CHIP_ID_BCM4716: + case BCMA_CHIP_ID_BCM4748: + bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_80211, 0); + bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_MAC_GBIT, 0); + bcma_core_mips_set_irq_name(bus, 3, BCMA_CORE_USB20_HOST, 0); + bcma_core_mips_set_irq_name(bus, 4, BCMA_CORE_PCIE, 0); + bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_CHIPCOMMON, 0); + bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_I2S, 0); + break; + case BCMA_CHIP_ID_BCM5356: + case BCMA_CHIP_ID_BCM47162: + case BCMA_CHIP_ID_BCM53572: + bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_80211, 0); + bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_MAC_GBIT, 0); + bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_CHIPCOMMON, 0); + break; + case BCMA_CHIP_ID_BCM5357: + case BCMA_CHIP_ID_BCM4749: + bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_80211, 0); + bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_MAC_GBIT, 0); + bcma_core_mips_set_irq_name(bus, 3, BCMA_CORE_USB20_HOST, 0); + bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_CHIPCOMMON, 0); + bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_I2S, 0); + break; + case BCMA_CHIP_ID_BCM4706: + bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_PCIE, 0); + bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_4706_MAC_GBIT, + 0); + bcma_core_mips_set_irq_name(bus, 3, BCMA_CORE_PCIE, 1); + bcma_core_mips_set_irq_name(bus, 4, BCMA_CORE_USB20_HOST, 0); + bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_4706_CHIPCOMMON, + 0); + break; + default: + list_for_each_entry(core, &bus->cores, list) { + core->irq = bcma_core_irq(core); } + bcma_err(bus, + "Unknown device (0x%x) found, can not configure IRQs\n", + bus->chipinfo.id); } - bcma_info(bus, "IRQ reconfiguration done\n"); + bcma_debug(bus, "IRQ reconfiguration done\n"); bcma_core_mips_dump_irq(bus); - if (mcore->setup_done) - return; - - bcma_chipco_serial_init(&bus->drv_cc); - bcma_core_mips_flash_detect(mcore); mcore->setup_done = true; } diff --git a/drivers/bcma/driver_pci.c b/drivers/bcma/driver_pci.c index c39ee6d45850..cf7a476a519f 100644 --- a/drivers/bcma/driver_pci.c +++ b/drivers/bcma/driver_pci.c @@ -207,14 +207,14 @@ static void bcma_core_pci_config_fixup(struct bcma_drv_pci *pc) * Init. **************************************************/ -static void __devinit bcma_core_pci_clientmode_init(struct bcma_drv_pci *pc) +static void bcma_core_pci_clientmode_init(struct bcma_drv_pci *pc) { bcma_core_pci_fixcfg(pc); bcma_pcicore_serdes_workaround(pc); bcma_core_pci_config_fixup(pc); } -void __devinit bcma_core_pci_init(struct bcma_drv_pci *pc) +void bcma_core_pci_init(struct bcma_drv_pci *pc) { if (pc->setup_done) return; diff --git a/drivers/bcma/driver_pci_host.c b/drivers/bcma/driver_pci_host.c index 9baf886e82df..30629a3d44cc 100644 --- a/drivers/bcma/driver_pci_host.c +++ b/drivers/bcma/driver_pci_host.c @@ -24,7 +24,7 @@ #define BCMA_PCI_SLOT_MAX 16 #define PCI_CONFIG_SPACE_SIZE 256 -bool __devinit bcma_core_pci_is_in_hostmode(struct bcma_drv_pci *pc) +bool bcma_core_pci_is_in_hostmode(struct bcma_drv_pci *pc) { struct bcma_bus *bus = pc->core->bus; u16 chipid_top; @@ -35,11 +35,6 @@ bool __devinit bcma_core_pci_is_in_hostmode(struct bcma_drv_pci *pc) chipid_top != 0x5300) return false; - if (bus->sprom.boardflags_lo & BCMA_CORE_PCI_BFL_NOPCI) { - bcma_info(bus, "This PCI core is disabled and not working\n"); - return false; - } - bcma_core_enable(pc->core, 0); return !mips_busprobe32(tmp, pc->core->io_addr); @@ -99,19 +94,19 @@ static int bcma_extpci_read_config(struct bcma_drv_pci *pc, unsigned int dev, if (dev == 0) { /* we support only two functions on device 0 */ if (func > 1) - return -EINVAL; + goto out; /* accesses to config registers with offsets >= 256 * requires indirect access. */ if (off >= PCI_CONFIG_SPACE_SIZE) { addr = (func << 12); - addr |= (off & 0x0FFF); + addr |= (off & 0x0FFC); val = bcma_pcie_read_config(pc, addr); } else { addr = BCMA_CORE_PCI_PCICFG0; addr |= (func << 8); - addr |= (off & 0xfc); + addr |= (off & 0xFC); val = pcicore_read32(pc, addr); } } else { @@ -124,11 +119,9 @@ static int bcma_extpci_read_config(struct bcma_drv_pci *pc, unsigned int dev, goto out; if (mips_busprobe32(val, mmio)) { - val = 0xffffffff; + val = 0xFFFFFFFF; goto unmap; } - - val = readl(mmio); } val >>= (8 * (off & 3)); @@ -156,7 +149,7 @@ static int bcma_extpci_write_config(struct bcma_drv_pci *pc, unsigned int dev, const void *buf, int len) { int err = -EINVAL; - u32 addr = 0, val = 0; + u32 addr, val; void __iomem *mmio = 0; u16 chipid = pc->core->bus->chipinfo.id; @@ -164,16 +157,22 @@ static int bcma_extpci_write_config(struct bcma_drv_pci *pc, unsigned int dev, if (unlikely(len != 1 && len != 2 && len != 4)) goto out; if (dev == 0) { + /* we support only two functions on device 0 */ + if (func > 1) + goto out; + /* accesses to config registers with offsets >= 256 * requires indirect access. */ - if (off < PCI_CONFIG_SPACE_SIZE) { - addr = pc->core->addr + BCMA_CORE_PCI_PCICFG0; + if (off >= PCI_CONFIG_SPACE_SIZE) { + addr = (func << 12); + addr |= (off & 0x0FFC); + val = bcma_pcie_read_config(pc, addr); + } else { + addr = BCMA_CORE_PCI_PCICFG0; addr |= (func << 8); - addr |= (off & 0xfc); - mmio = ioremap_nocache(addr, sizeof(val)); - if (!mmio) - goto out; + addr |= (off & 0xFC); + val = pcicore_read32(pc, addr); } } else { addr = bcma_get_cfgspace_addr(pc, dev, func, off); @@ -185,19 +184,17 @@ static int bcma_extpci_write_config(struct bcma_drv_pci *pc, unsigned int dev, goto out; if (mips_busprobe32(val, mmio)) { - val = 0xffffffff; + val = 0xFFFFFFFF; goto unmap; } } switch (len) { case 1: - val = readl(mmio); val &= ~(0xFF << (8 * (off & 3))); val |= *((const u8 *)buf) << (8 * (off & 3)); break; case 2: - val = readl(mmio); val &= ~(0xFFFF << (8 * (off & 3))); val |= *((const u16 *)buf) << (8 * (off & 3)); break; @@ -205,13 +202,14 @@ static int bcma_extpci_write_config(struct bcma_drv_pci *pc, unsigned int dev, val = *((const u32 *)buf); break; } - if (dev == 0 && !addr) { + if (dev == 0) { /* accesses to config registers with offsets >= 256 * requires indirect access. */ - addr = (func << 12); - addr |= (off & 0x0FFF); - bcma_pcie_write_config(pc, addr, val); + if (off >= PCI_CONFIG_SPACE_SIZE) + bcma_pcie_write_config(pc, addr, val); + else + pcicore_write32(pc, addr, val); } else { writel(val, mmio); @@ -269,10 +267,9 @@ static int bcma_core_pci_hostmode_write_config(struct pci_bus *bus, } /* return cap_offset if requested capability exists in the PCI config space */ -static u8 __devinit bcma_find_pci_capability(struct bcma_drv_pci *pc, - unsigned int dev, - unsigned int func, u8 req_cap_id, - unsigned char *buf, u32 *buflen) +static u8 bcma_find_pci_capability(struct bcma_drv_pci *pc, unsigned int dev, + unsigned int func, u8 req_cap_id, + unsigned char *buf, u32 *buflen) { u8 cap_id; u8 cap_ptr = 0; @@ -282,7 +279,7 @@ static u8 __devinit bcma_find_pci_capability(struct bcma_drv_pci *pc, /* check for Header type 0 */ bcma_extpci_read_config(pc, dev, func, PCI_HEADER_TYPE, &byte_val, sizeof(u8)); - if ((byte_val & 0x7f) != PCI_HEADER_TYPE_NORMAL) + if ((byte_val & 0x7F) != PCI_HEADER_TYPE_NORMAL) return cap_ptr; /* check if the capability pointer field exists */ @@ -339,7 +336,7 @@ static u8 __devinit bcma_find_pci_capability(struct bcma_drv_pci *pc, * Retry Status (CRS) Completion Status to software then * enable the feature. */ -static void __devinit bcma_core_pci_enable_crs(struct bcma_drv_pci *pc) +static void bcma_core_pci_enable_crs(struct bcma_drv_pci *pc) { struct bcma_bus *bus = pc->core->bus; u8 cap_ptr, root_ctrl, root_cap, dev; @@ -386,7 +383,7 @@ static void __devinit bcma_core_pci_enable_crs(struct bcma_drv_pci *pc) } } -void __devinit bcma_core_pci_hostmode_init(struct bcma_drv_pci *pc) +void bcma_core_pci_hostmode_init(struct bcma_drv_pci *pc) { struct bcma_bus *bus = pc->core->bus; struct bcma_drv_pci_host *pc_host; @@ -396,12 +393,19 @@ void __devinit bcma_core_pci_hostmode_init(struct bcma_drv_pci *pc) bcma_info(bus, "PCIEcore in host mode found\n"); + if (bus->sprom.boardflags_lo & BCMA_CORE_PCI_BFL_NOPCI) { + bcma_info(bus, "This PCIE core is disabled and not working\n"); + return; + } + pc_host = kzalloc(sizeof(*pc_host), GFP_KERNEL); if (!pc_host) { bcma_err(bus, "can not allocate memory"); return; } + spin_lock_init(&pc_host->cfgspace_lock); + pc->host_controller = pc_host; pc_host->pci_controller.io_resource = &pc_host->io_resource; pc_host->pci_controller.mem_resource = &pc_host->mem_resource; @@ -427,7 +431,7 @@ void __devinit bcma_core_pci_hostmode_init(struct bcma_drv_pci *pc) /* Reset RC */ usleep_range(3000, 5000); pcicore_write32(pc, BCMA_CORE_PCI_CTL, BCMA_CORE_PCI_CTL_RST_OE); - usleep_range(1000, 2000); + msleep(50); pcicore_write32(pc, BCMA_CORE_PCI_CTL, BCMA_CORE_PCI_CTL_RST | BCMA_CORE_PCI_CTL_RST_OE); @@ -452,6 +456,8 @@ void __devinit bcma_core_pci_hostmode_init(struct bcma_drv_pci *pc) pc_host->mem_resource.start = BCMA_SOC_PCI_MEM; pc_host->mem_resource.end = BCMA_SOC_PCI_MEM + BCMA_SOC_PCI_MEM_SZ - 1; + pc_host->io_resource.start = 0x100; + pc_host->io_resource.end = 0x47F; pci_membase_1G = BCMA_SOC_PCIE_DMA_H32; pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI0, tmp | BCMA_SOC_PCI_MEM); @@ -459,6 +465,8 @@ void __devinit bcma_core_pci_hostmode_init(struct bcma_drv_pci *pc) pc_host->mem_resource.start = BCMA_SOC_PCI1_MEM; pc_host->mem_resource.end = BCMA_SOC_PCI1_MEM + BCMA_SOC_PCI_MEM_SZ - 1; + pc_host->io_resource.start = 0x480; + pc_host->io_resource.end = 0x7FF; pci_membase_1G = BCMA_SOC_PCIE1_DMA_H32; pc_host->host_cfg_addr = BCMA_SOC_PCI1_CFG; pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI0, @@ -485,6 +493,17 @@ void __devinit bcma_core_pci_hostmode_init(struct bcma_drv_pci *pc) bcma_core_pci_enable_crs(pc); + if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706 || + bus->chipinfo.id == BCMA_CHIP_ID_BCM4716) { + u16 val16; + bcma_extpci_read_config(pc, 0, 0, BCMA_CORE_PCI_CFG_DEVCTRL, + &val16, sizeof(val16)); + val16 |= (2 << 5); /* Max payload size of 512 */ + val16 |= (2 << 12); /* MRRS 512 */ + bcma_extpci_write_config(pc, 0, 0, BCMA_CORE_PCI_CFG_DEVCTRL, + &val16, sizeof(val16)); + } + /* Enable PCI bridge BAR0 memory & master access */ tmp = PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; bcma_extpci_write_config(pc, 0, 0, PCI_COMMAND, &tmp, sizeof(tmp)); @@ -534,7 +553,7 @@ DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, bcma_core_pci_fixup_pcibridge); static void bcma_core_pci_fixup_addresses(struct pci_dev *dev) { struct resource *res; - int pos; + int pos, err; if (dev->bus->ops->read != bcma_core_pci_hostmode_read_config) { /* This is not a device on the PCI-core bridge. */ @@ -547,8 +566,12 @@ static void bcma_core_pci_fixup_addresses(struct pci_dev *dev) for (pos = 0; pos < 6; pos++) { res = &dev->resource[pos]; - if (res->flags & (IORESOURCE_IO | IORESOURCE_MEM)) - pci_assign_resource(dev, pos); + if (res->flags & (IORESOURCE_IO | IORESOURCE_MEM)) { + err = pci_assign_resource(dev, pos); + if (err) + pr_err("PCI: Problem fixing up the addresses on %s\n", + pci_name(dev)); + } } } DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, bcma_core_pci_fixup_addresses); @@ -569,7 +592,7 @@ int bcma_core_pci_plat_dev_init(struct pci_dev *dev) pr_info("PCI: Fixing up device %s\n", pci_name(dev)); /* Fix up interrupt lines */ - dev->irq = bcma_core_mips_irq(pc_host->pdev->core) + 2; + dev->irq = bcma_core_irq(pc_host->pdev->core); pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq); return 0; @@ -588,6 +611,6 @@ int bcma_core_pci_pcibios_map_irq(const struct pci_dev *dev) pc_host = container_of(dev->bus->ops, struct bcma_drv_pci_host, pci_ops); - return bcma_core_mips_irq(pc_host->pdev->core) + 2; + return bcma_core_irq(pc_host->pdev->core); } EXPORT_SYMBOL(bcma_core_pci_pcibios_map_irq); diff --git a/drivers/bcma/host_pci.c b/drivers/bcma/host_pci.c index b6b4b5ebd4c2..fbf2759e7e4e 100644 --- a/drivers/bcma/host_pci.c +++ b/drivers/bcma/host_pci.c @@ -155,8 +155,8 @@ static const struct bcma_host_ops bcma_host_pci_ops = { .awrite32 = bcma_host_pci_awrite32, }; -static int __devinit bcma_host_pci_probe(struct pci_dev *dev, - const struct pci_device_id *id) +static int bcma_host_pci_probe(struct pci_dev *dev, + const struct pci_device_id *id) { struct bcma_bus *bus; int err = -ENOMEM; @@ -226,7 +226,7 @@ err_kfree_bus: return err; } -static void __devexit bcma_host_pci_remove(struct pci_dev *dev) +static void bcma_host_pci_remove(struct pci_dev *dev) { struct bcma_bus *bus = pci_get_drvdata(dev); @@ -238,7 +238,7 @@ static void __devexit bcma_host_pci_remove(struct pci_dev *dev) pci_set_drvdata(dev, NULL); } -#ifdef CONFIG_PM +#ifdef CONFIG_PM_SLEEP static int bcma_host_pci_suspend(struct device *dev) { struct pci_dev *pdev = to_pci_dev(dev); @@ -261,11 +261,11 @@ static SIMPLE_DEV_PM_OPS(bcma_pm_ops, bcma_host_pci_suspend, bcma_host_pci_resume); #define BCMA_PM_OPS (&bcma_pm_ops) -#else /* CONFIG_PM */ +#else /* CONFIG_PM_SLEEP */ #define BCMA_PM_OPS NULL -#endif /* CONFIG_PM */ +#endif /* CONFIG_PM_SLEEP */ static DEFINE_PCI_DEVICE_TABLE(bcma_pci_bridge_tbl) = { { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x0576) }, @@ -284,7 +284,7 @@ static struct pci_driver bcma_pci_bridge_driver = { .name = "bcma-pci-bridge", .id_table = bcma_pci_bridge_tbl, .probe = bcma_host_pci_probe, - .remove = __devexit_p(bcma_host_pci_remove), + .remove = bcma_host_pci_remove, .driver.pm = BCMA_PM_OPS, }; diff --git a/drivers/bcma/main.c b/drivers/bcma/main.c index d865470bc951..9a6188add590 100644 --- a/drivers/bcma/main.c +++ b/drivers/bcma/main.c @@ -81,6 +81,18 @@ struct bcma_device *bcma_find_core(struct bcma_bus *bus, u16 coreid) } EXPORT_SYMBOL_GPL(bcma_find_core); +struct bcma_device *bcma_find_core_unit(struct bcma_bus *bus, u16 coreid, + u8 unit) +{ + struct bcma_device *core; + + list_for_each_entry(core, &bus->cores, list) { + if (core->id.id == coreid && core->core_unit == unit) + return core; + } + return NULL; +} + static void bcma_release_core_dev(struct device *dev) { struct bcma_device *core = container_of(dev, struct bcma_device, dev); @@ -137,6 +149,14 @@ static int bcma_register_cores(struct bcma_bus *bus) dev_id++; } +#ifdef CONFIG_BCMA_DRIVER_MIPS + if (bus->drv_cc.pflash.present) { + err = platform_device_register(&bcma_pflash_dev); + if (err) + bcma_err(bus, "Error registering parallel flash\n"); + } +#endif + #ifdef CONFIG_BCMA_SFLASH if (bus->drv_cc.sflash.present) { err = platform_device_register(&bcma_sflash_dev); @@ -152,6 +172,17 @@ static int bcma_register_cores(struct bcma_bus *bus) bcma_err(bus, "Error registering NAND flash\n"); } #endif + err = bcma_gpio_init(&bus->drv_cc); + if (err == -ENOTSUPP) + bcma_debug(bus, "GPIO driver not activated\n"); + else if (err) + bcma_err(bus, "Error registering GPIO driver: %i\n", err); + + if (bus->hosttype == BCMA_HOSTTYPE_SOC) { + err = bcma_chipco_watchdog_register(&bus->drv_cc); + if (err) + bcma_err(bus, "Error registering watchdog driver\n"); + } return 0; } @@ -165,9 +196,11 @@ static void bcma_unregister_cores(struct bcma_bus *bus) if (core->dev_registered) device_unregister(&core->dev); } + if (bus->hosttype == BCMA_HOSTTYPE_SOC) + platform_device_unregister(bus->drv_cc.watchdog); } -int __devinit bcma_bus_register(struct bcma_bus *bus) +int bcma_bus_register(struct bcma_bus *bus) { int err; struct bcma_device *core; @@ -183,6 +216,20 @@ int __devinit bcma_bus_register(struct bcma_bus *bus) return -1; } + /* Early init CC core */ + core = bcma_find_core(bus, bcma_cc_core_id(bus)); + if (core) { + bus->drv_cc.core = core; + bcma_core_chipcommon_early_init(&bus->drv_cc); + } + + /* Try to get SPROM */ + err = bcma_sprom_get(bus); + if (err == -ENOENT) { + bcma_err(bus, "No SPROM available\n"); + } else if (err) + bcma_err(bus, "Failed to get SPROM: %d\n", err); + /* Init CC core */ core = bcma_find_core(bus, bcma_cc_core_id(bus)); if (core) { @@ -198,10 +245,17 @@ int __devinit bcma_bus_register(struct bcma_bus *bus) } /* Init PCIE core */ - core = bcma_find_core(bus, BCMA_CORE_PCIE); + core = bcma_find_core_unit(bus, BCMA_CORE_PCIE, 0); if (core) { - bus->drv_pci.core = core; - bcma_core_pci_init(&bus->drv_pci); + bus->drv_pci[0].core = core; + bcma_core_pci_init(&bus->drv_pci[0]); + } + + /* Init PCIE core */ + core = bcma_find_core_unit(bus, BCMA_CORE_PCIE, 1); + if (core) { + bus->drv_pci[1].core = core; + bcma_core_pci_init(&bus->drv_pci[1]); } /* Init GBIT MAC COMMON core */ @@ -211,13 +265,6 @@ int __devinit bcma_bus_register(struct bcma_bus *bus) bcma_core_gmac_cmn_init(&bus->drv_gmac_cmn); } - /* Try to get SPROM */ - err = bcma_sprom_get(bus); - if (err == -ENOENT) { - bcma_err(bus, "No SPROM available\n"); - } else if (err) - bcma_err(bus, "Failed to get SPROM: %d\n", err); - /* Register found cores */ bcma_register_cores(bus); @@ -229,6 +276,13 @@ int __devinit bcma_bus_register(struct bcma_bus *bus) void bcma_bus_unregister(struct bcma_bus *bus) { struct bcma_device *cores[3]; + int err; + + err = bcma_gpio_unregister(&bus->drv_cc); + if (err == -EBUSY) + bcma_err(bus, "Some GPIOs are still in use.\n"); + else if (err) + bcma_err(bus, "Can not unregister GPIO driver: %i\n", err); cores[0] = bcma_find_core(bus, BCMA_CORE_MIPS_74K); cores[1] = bcma_find_core(bus, BCMA_CORE_PCIE); @@ -275,18 +329,18 @@ int __init bcma_bus_early_register(struct bcma_bus *bus, return -1; } - /* Init CC core */ + /* Early init CC core */ core = bcma_find_core(bus, bcma_cc_core_id(bus)); if (core) { bus->drv_cc.core = core; - bcma_core_chipcommon_init(&bus->drv_cc); + bcma_core_chipcommon_early_init(&bus->drv_cc); } - /* Init MIPS core */ + /* Early init MIPS core */ core = bcma_find_core(bus, BCMA_CORE_MIPS_74K); if (core) { bus->drv_mips.core = core; - bcma_core_mips_init(&bus->drv_mips); + bcma_core_mips_early_init(&bus->drv_mips); } bcma_info(bus, "Early bus registered\n"); diff --git a/drivers/bcma/sprom.c b/drivers/bcma/sprom.c index 0d546b64be34..4adf9ef9a113 100644 --- a/drivers/bcma/sprom.c +++ b/drivers/bcma/sprom.c @@ -595,8 +595,11 @@ int bcma_sprom_get(struct bcma_bus *bus) bcma_chipco_bcm4331_ext_pa_lines_ctl(&bus->drv_cc, true); err = bcma_sprom_valid(sprom); - if (err) + if (err) { + bcma_warn(bus, "invalid sprom read from the PCIe card, try to use fallback sprom\n"); + err = bcma_fill_sprom_with_fallback(bus, &bus->sprom); goto out; + } bcma_sprom_extract_r8(bus, sprom); |