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authorWang Zhenyu <zhenyu.z.wang@intel.com>2007-06-10 15:58:19 +1000
committerDave Airlie <airlied@linux.ie>2007-06-10 15:58:19 +1000
commitdc7a93190c21edbf3ed23e678ad04f852b9cff28 (patch)
treecc05781518d289b91b4da869881273205fe7ccb1 /drivers/char/drm/drm_pciids.h
parent2f4042b186b9bfe82f48fe801619c6c285c16bef (diff)
downloadlinux-next-dc7a93190c21edbf3ed23e678ad04f852b9cff28.tar.gz
drm/i915: Add support for the G33, Q33, and Q35 chipsets.
These require that the status page be referenced by a pointer in GTT, rather than phsyical memory. So, we have the X Server allocate that memory and tell us the address, instead. Signed-off-by: Dave Airlie <airlied@linux.ie>
Diffstat (limited to 'drivers/char/drm/drm_pciids.h')
-rw-r--r--drivers/char/drm/drm_pciids.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/char/drm/drm_pciids.h b/drivers/char/drm/drm_pciids.h
index e908462051fd..aa6335032d1e 100644
--- a/drivers/char/drm/drm_pciids.h
+++ b/drivers/char/drm/drm_pciids.h
@@ -305,6 +305,9 @@
{0x8086, 0x2982, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
{0x8086, 0x2992, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
{0x8086, 0x29a2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
+ {0x8086, 0x29b2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
+ {0x8086, 0x29c2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
+ {0x8086, 0x29d2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
{0x8086, 0x2a02, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
{0x8086, 0x2a12, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
{0, 0, 0}