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authorTomasz Figa <t.figa@samsung.com>2012-10-11 10:11:15 +0200
committerLinus Walleij <linus.walleij@linaro.org>2012-10-15 09:10:12 +0200
commit1b6056d6db2426cd612f03dabacf655ecb6a27ae (patch)
treecc7146778c548af33a845e2523ad273ec7410774 /drivers/pinctrl/pinctrl-exynos.h
parent6defe9a0ddc59aa2302473aa3c8b3fdb543fdc1b (diff)
downloadlinux-next-1b6056d6db2426cd612f03dabacf655ecb6a27ae.tar.gz
pinctrl: samsung: Include bank-specific eint offset in bank struct
Some SoCs, like Exynos4x12, have non-sequential layout of EINT control registers and so current way of calculating register addresses does not work correctly for them. This patch adds eint_offset field to samsung_pin_bank struct and modifies the driver to use it instead of calculating the offsets from bank index. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Reviewed-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Thomas Abraham <thomas.abraham@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'drivers/pinctrl/pinctrl-exynos.h')
-rw-r--r--drivers/pinctrl/pinctrl-exynos.h3
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/pinctrl/pinctrl-exynos.h b/drivers/pinctrl/pinctrl-exynos.h
index 2de4a2936e9c..5d8e380fbadf 100644
--- a/drivers/pinctrl/pinctrl-exynos.h
+++ b/drivers/pinctrl/pinctrl-exynos.h
@@ -59,7 +59,7 @@
.name = id \
}
-#define EXYNOS_PIN_BANK_EINTG(pins, reg, id) \
+#define EXYNOS_PIN_BANK_EINTG(pins, reg, id, offs) \
{ \
.pctl_offset = reg, \
.nr_pins = pins, \
@@ -69,6 +69,7 @@
.conpdn_width = 2, \
.pudpdn_width = 2, \
.eint_type = EINT_TYPE_GPIO, \
+ .eint_offset = offs, \
.name = id \
}