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| author | David S. Miller <davem@sunset.davemloft.net> | 2007-08-08 17:11:39 -0700 |
|---|---|---|
| committer | David S. Miller <davem@sunset.davemloft.net> | 2007-08-08 17:33:45 -0700 |
| commit | 6c70b6fc7b6fc321636a014082d9e32333da1f80 (patch) | |
| tree | ff0e52bb7ba43b058b7cbb88b952fd268fbe3ad2 /include/asm-sparc64/xor.h | |
| parent | 68c9f9fd336dc7e793cecad25f8ac40ccaa7a256 (diff) | |
| download | linux-next-6c70b6fc7b6fc321636a014082d9e32333da1f80.tar.gz | |
[SPARC64]: Do not assume sun4v chips have load-twin/store-init support.
Check the cpu type in the OBP device tree before committing to
using the optimized Niagara memcpy and memset implementation.
If we don't recognize the cpu type, use a completely generic
version.
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'include/asm-sparc64/xor.h')
| -rw-r--r-- | include/asm-sparc64/xor.h | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/include/asm-sparc64/xor.h b/include/asm-sparc64/xor.h index 8ce3f1813e28..a0233884fc94 100644 --- a/include/asm-sparc64/xor.h +++ b/include/asm-sparc64/xor.h @@ -63,4 +63,8 @@ static struct xor_block_template xor_block_niagara = { /* For VIS for everything except Niagara. */ #define XOR_SELECT_TEMPLATE(FASTEST) \ - (tlb_type == hypervisor ? &xor_block_niagara : &xor_block_VIS) + ((tlb_type == hypervisor && \ + (sun4v_chip_type == SUN4V_CHIP_NIAGARA1 || \ + sun4v_chip_type == SUN4V_CHIP_NIAGARA2)) ? \ + &xor_block_niagara : \ + &xor_block_VIS) |