diff options
| author | Guy Levi <guyle@mellanox.com> | 2017-10-19 08:25:53 +0300 |
|---|---|---|
| committer | Doug Ledford <dledford@redhat.com> | 2017-10-25 14:17:06 -0400 |
| commit | 7a0c8f4244e9ec7a630563d294b211342b46223d (patch) | |
| tree | f5db884ceca6261ec04e0d70ef8174e0ac3a92fd /include/linux/mlx5/cq.h | |
| parent | de57f2ad06d5bf01015b955600cbfc77059b2b6e (diff) | |
| download | linux-next-7a0c8f4244e9ec7a630563d294b211342b46223d.tar.gz | |
IB/mlx5: Support padded 128B CQE feature
In some benchmarks and some CPU architectures, writing the CQE on a full
cache line size improves performance by saving memory access operations
(read-modify-write) relative to partial cache line change. This patch
lets the user to configure the device to pad the CQE up to 128B in case
its content is less than 128B. Currently the driver supports only padding
for a CQE size of 128B.
Signed-off-by: Guy Levi <guyle@mellanox.com>
Reviewed-by: Mark Bloch <markb@mellanox.com>
Signed-off-by: Leon Romanovsky <leon@kernel.org>
Signed-off-by: Doug Ledford <dledford@redhat.com>
Diffstat (limited to 'include/linux/mlx5/cq.h')
| -rw-r--r-- | include/linux/mlx5/cq.h | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/include/linux/mlx5/cq.h b/include/linux/mlx5/cq.h index 95898847c7d4..cc718e245b1e 100644 --- a/include/linux/mlx5/cq.h +++ b/include/linux/mlx5/cq.h @@ -125,11 +125,13 @@ struct mlx5_cq_modify_params { enum { CQE_SIZE_64 = 0, CQE_SIZE_128 = 1, + CQE_SIZE_128_PAD = 2, }; -static inline int cqe_sz_to_mlx_sz(u8 size) +static inline int cqe_sz_to_mlx_sz(u8 size, int padding_128_en) { - return size == 64 ? CQE_SIZE_64 : CQE_SIZE_128; + return padding_128_en ? CQE_SIZE_128_PAD : + size == 64 ? CQE_SIZE_64 : CQE_SIZE_128; } static inline void mlx5_cq_set_ci(struct mlx5_core_cq *cq) |