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authorludovic.desroches@atmel.com <ludovic.desroches@atmel.com>2015-09-17 10:16:19 +0200
committerUlf Hansson <ulf.hansson@linaro.org>2015-10-08 19:55:05 +0200
commitaf951761d01c89eea8f1dcccf8010218e4b55817 (patch)
tree41f5fa35918daed8aa7353fe7123bd83b224ada1 /net/sched/em_cmp.c
parent2162d9f41e7c4778b96b8e3b97adcedbadc861f1 (diff)
downloadlinux-next-af951761d01c89eea8f1dcccf8010218e4b55817.tar.gz
mmc: sdhci: add quirk SDHCI_QUIRK2_NEED_DELAY_AFTER_INT_CLK_RST
The Atmel sdhci device needs a new quirk. sdhci_set_clock set the Clock Control Register to 0 before computing the new value and writing it. It disables the internal clock which causes a reset mecanism. If we write the new value before this reset mecanism is done, it will prevent the stabilisation of the internal clock, so a delay is needed. This delay is about 2-3 cycles of the base clock. To be safe, a 1 ms delay is used. Signed-off-by: Ludovic Desroches <ludovic.desroches@atmel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Diffstat (limited to 'net/sched/em_cmp.c')
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