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| author | Shengjiu Wang <shengjiu.wang@nxp.com> | 2020-04-24 10:01:38 +0800 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2020-04-24 11:31:04 +0100 |
| commit | c38b608504aa1ad8bfa00d85abd61cffad57f27f (patch) | |
| tree | 505a54af72fd013d78b9e31cfcc6b8e813ae2af5 /sound/soc/fsl/fsl_esai.c | |
| parent | 41d91ec3de8a90167159275bde7ed65768723556 (diff) | |
| download | linux-next-c38b608504aa1ad8bfa00d85abd61cffad57f27f.tar.gz | |
ASoC: wm8962: set CLOCKING2 as non-volatile register
Previously CLOCKING2 is set as a volatile register, but cause
issue at suspend & resume, that some bits of CLOCKING2 is not
restored at resume, for example SYSCLK_SRC bits, then the output
clock is wrong.
The volatile property is caused by CLASSD_CLK_DIV bits,
which are controlled by the chip itself. But the datasheet
claims these are read only and protected by the security key,
and they are not read by the driver at all.
So it should be safe to change CLOCKING2 to be non-volatile.
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Acked-by: Charles Keepax <ckeepax@opensource.cirrus.com>
Link: https://lore.kernel.org/r/6d25d5b36d4b9aeb8655b5e947dad52214e34177.1587693523.git.shengjiu.wang@nxp.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'sound/soc/fsl/fsl_esai.c')
0 files changed, 0 insertions, 0 deletions