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author | Shengjiu Wang <shengjiu.wang@nxp.com> | 2019-01-18 14:26:46 +0000 |
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committer | Mark Brown <broonie@kernel.org> | 2019-01-18 18:09:15 +0000 |
commit | e412fcb0db5c44a3450ca678b281ea9332e6bf82 (patch) | |
tree | a38879255b15631a8731b3207e8d66a679f3131f /sound/soc/fsl | |
parent | 7c7e2d6a9ca3c74ba7ed4da2a75916b2f9ae38f0 (diff) | |
download | linux-next-e412fcb0db5c44a3450ca678b281ea9332e6bf82.tar.gz |
ASoC: fsl_sai: Remove expensive print in irq handler
When stopping audio, ASoC will first stop DMA then CPU DAI.
Sometimes there is a delay between DMA stop and CPU DAI stop, which
triggers an underrun error. Now, because of the delay introduced
by dev_err another underrun error will occur causing a vicious circle
making impossible to stop CPU DAI.
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'sound/soc/fsl')
-rw-r--r-- | sound/soc/fsl/fsl_sai.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/sound/soc/fsl/fsl_sai.c b/sound/soc/fsl/fsl_sai.c index 4163f2cfc06f..db9e0872f73d 100644 --- a/sound/soc/fsl/fsl_sai.c +++ b/sound/soc/fsl/fsl_sai.c @@ -62,10 +62,10 @@ static irqreturn_t fsl_sai_isr(int irq, void *devid) dev_dbg(dev, "isr: Start of Tx word detected\n"); if (flags & FSL_SAI_CSR_SEF) - dev_warn(dev, "isr: Tx Frame sync error detected\n"); + dev_dbg(dev, "isr: Tx Frame sync error detected\n"); if (flags & FSL_SAI_CSR_FEF) { - dev_warn(dev, "isr: Transmit underrun detected\n"); + dev_dbg(dev, "isr: Transmit underrun detected\n"); /* FIFO reset for safety */ xcsr |= FSL_SAI_CSR_FR; } @@ -96,10 +96,10 @@ irq_rx: dev_dbg(dev, "isr: Start of Rx word detected\n"); if (flags & FSL_SAI_CSR_SEF) - dev_warn(dev, "isr: Rx Frame sync error detected\n"); + dev_dbg(dev, "isr: Rx Frame sync error detected\n"); if (flags & FSL_SAI_CSR_FEF) { - dev_warn(dev, "isr: Receive overflow detected\n"); + dev_dbg(dev, "isr: Receive overflow detected\n"); /* FIFO reset for safety */ xcsr |= FSL_SAI_CSR_FR; } |