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Diffstat (limited to 'arch/mips/txx9/rbtx4927/setup.c')
-rw-r--r--arch/mips/txx9/rbtx4927/setup.c703
1 files changed, 703 insertions, 0 deletions
diff --git a/arch/mips/txx9/rbtx4927/setup.c b/arch/mips/txx9/rbtx4927/setup.c
new file mode 100644
index 000000000000..df1b6e99b666
--- /dev/null
+++ b/arch/mips/txx9/rbtx4927/setup.c
@@ -0,0 +1,703 @@
+/*
+ * Toshiba rbtx4927 specific setup
+ *
+ * Author: MontaVista Software, Inc.
+ * source@mvista.com
+ *
+ * Copyright 2001-2002 MontaVista Software Inc.
+ *
+ * Copyright (C) 1996, 97, 2001, 04 Ralf Baechle (ralf@linux-mips.org)
+ * Copyright (C) 2000 RidgeRun, Inc.
+ * Author: RidgeRun, Inc.
+ * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
+ *
+ * Copyright 2001 MontaVista Software Inc.
+ * Author: jsun@mvista.com or jsun@junsun.net
+ *
+ * Copyright 2002 MontaVista Software Inc.
+ * Author: Michael Pruznick, michael_pruznick@mvista.com
+ *
+ * Copyright (C) 2000-2001 Toshiba Corporation
+ *
+ * Copyright (C) 2004 MontaVista Software Inc.
+ * Author: Manish Lachwani, mlachwani@mvista.com
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+ * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/ioport.h>
+#include <linux/interrupt.h>
+#include <linux/pci.h>
+#include <linux/pm.h>
+#include <linux/platform_device.h>
+#include <linux/clk.h>
+
+#include <asm/bootinfo.h>
+#include <asm/io.h>
+#include <asm/processor.h>
+#include <asm/reboot.h>
+#include <asm/time.h>
+#include <asm/txx9tmr.h>
+#ifdef CONFIG_TOSHIBA_FPCIB0
+#include <asm/txx9/smsc_fdc37m81x.h>
+#endif
+#include <asm/txx9/rbtx4927.h>
+#ifdef CONFIG_SERIAL_TXX9
+#include <linux/serial_core.h>
+#endif
+
+/* These functions are used for rebooting or halting the machine*/
+extern void toshiba_rbtx4927_restart(char *command);
+extern void toshiba_rbtx4927_halt(void);
+extern void toshiba_rbtx4927_power_off(void);
+
+int tx4927_using_backplane = 0;
+
+extern void toshiba_rbtx4927_irq_setup(void);
+
+char *prom_getcmdline(void);
+
+#ifdef CONFIG_PCI
+#undef TX4927_SUPPORT_COMMAND_IO
+#undef TX4927_SUPPORT_PCI_66
+int tx4927_cpu_clock = 100000000; /* 100MHz */
+unsigned long mips_pci_io_base;
+unsigned long mips_pci_io_size;
+unsigned long mips_pci_mem_base;
+unsigned long mips_pci_mem_size;
+/* for legacy I/O, PCI I/O PCI Bus address must be 0 */
+unsigned long mips_pci_io_pciaddr = 0;
+unsigned long mips_memory_upper;
+static int tx4927_ccfg_toeon = 1;
+static int tx4927_pcic_trdyto = 0; /* default: disabled */
+unsigned long tx4927_ce_base[8];
+int tx4927_pci66 = 0; /* 0:auto */
+#endif
+
+char *toshiba_name = "";
+
+#ifdef CONFIG_PCI
+extern struct pci_controller tx4927_controller;
+
+static struct pci_dev *fake_pci_dev(struct pci_controller *hose,
+ int top_bus, int busnr, int devfn)
+{
+ static struct pci_dev dev;
+ static struct pci_bus bus;
+
+ dev.sysdata = (void *)hose;
+ dev.devfn = devfn;
+ bus.number = busnr;
+ bus.ops = hose->pci_ops;
+ bus.parent = NULL;
+ dev.bus = &bus;
+
+ return &dev;
+}
+
+#define EARLY_PCI_OP(rw, size, type) \
+static int early_##rw##_config_##size(struct pci_controller *hose, \
+ int top_bus, int bus, int devfn, int offset, type value) \
+{ \
+ return pci_##rw##_config_##size( \
+ fake_pci_dev(hose, top_bus, bus, devfn), \
+ offset, value); \
+}
+
+EARLY_PCI_OP(read, byte, u8 *)
+EARLY_PCI_OP(read, dword, u32 *)
+EARLY_PCI_OP(write, byte, u8)
+EARLY_PCI_OP(write, dword, u32)
+
+static int __init tx4927_pcibios_init(void)
+{
+ unsigned int id;
+ u32 pci_devfn;
+ int devfn_start = 0;
+ int devfn_stop = 0xff;
+ int busno = 0; /* One bus on the Toshiba */
+ struct pci_controller *hose = &tx4927_controller;
+
+ for (pci_devfn = devfn_start; pci_devfn < devfn_stop; pci_devfn++) {
+ early_read_config_dword(hose, busno, busno, pci_devfn,
+ PCI_VENDOR_ID, &id);
+
+ if (id == 0xffffffff) {
+ continue;
+ }
+
+ if (id == 0x94601055) {
+ u8 v08_64;
+ u32 v32_b0;
+ u8 v08_e1;
+
+ early_read_config_byte(hose, busno, busno,
+ pci_devfn, 0x64, &v08_64);
+ early_read_config_dword(hose, busno, busno,
+ pci_devfn, 0xb0, &v32_b0);
+ early_read_config_byte(hose, busno, busno,
+ pci_devfn, 0xe1, &v08_e1);
+
+ /* serial irq control */
+ v08_64 = 0xd0;
+
+ /* serial irq pin */
+ v32_b0 |= 0x00010000;
+
+ /* ide irq on isa14 */
+ v08_e1 &= 0xf0;
+ v08_e1 |= 0x0d;
+
+ early_write_config_byte(hose, busno, busno,
+ pci_devfn, 0x64, v08_64);
+ early_write_config_dword(hose, busno, busno,
+ pci_devfn, 0xb0, v32_b0);
+ early_write_config_byte(hose, busno, busno,
+ pci_devfn, 0xe1, v08_e1);
+ }
+
+ if (id == 0x91301055) {
+ u8 v08_04;
+ u8 v08_09;
+ u8 v08_41;
+ u8 v08_43;
+ u8 v08_5c;
+
+ early_read_config_byte(hose, busno, busno,
+ pci_devfn, 0x04, &v08_04);
+ early_read_config_byte(hose, busno, busno,
+ pci_devfn, 0x09, &v08_09);
+ early_read_config_byte(hose, busno, busno,
+ pci_devfn, 0x41, &v08_41);
+ early_read_config_byte(hose, busno, busno,
+ pci_devfn, 0x43, &v08_43);
+ early_read_config_byte(hose, busno, busno,
+ pci_devfn, 0x5c, &v08_5c);
+
+ /* enable ide master/io */
+ v08_04 |= (PCI_COMMAND_MASTER | PCI_COMMAND_IO);
+
+ /* enable ide native mode */
+ v08_09 |= 0x05;
+
+ /* enable primary ide */
+ v08_41 |= 0x80;
+
+ /* enable secondary ide */
+ v08_43 |= 0x80;
+
+ /*
+ * !!! DO NOT REMOVE THIS COMMENT IT IS REQUIRED BY SMSC !!!
+ *
+ * This line of code is intended to provide the user with a work
+ * around solution to the anomalies cited in SMSC's anomaly sheet
+ * entitled, "SLC90E66 Functional Rev.J_0.1 Anomalies"".
+ *
+ * !!! DO NOT REMOVE THIS COMMENT IT IS REQUIRED BY SMSC !!!
+ */
+ v08_5c |= 0x01;
+
+ early_write_config_byte(hose, busno, busno,
+ pci_devfn, 0x5c, v08_5c);
+ early_write_config_byte(hose, busno, busno,
+ pci_devfn, 0x04, v08_04);
+ early_write_config_byte(hose, busno, busno,
+ pci_devfn, 0x09, v08_09);
+ early_write_config_byte(hose, busno, busno,
+ pci_devfn, 0x41, v08_41);
+ early_write_config_byte(hose, busno, busno,
+ pci_devfn, 0x43, v08_43);
+ }
+
+ }
+
+ register_pci_controller(&tx4927_controller);
+ return 0;
+}
+
+arch_initcall(tx4927_pcibios_init);
+
+extern struct resource pci_io_resource;
+extern struct resource pci_mem_resource;
+
+void __init tx4927_pci_setup(void)
+{
+ static int called = 0;
+ extern unsigned int tx4927_get_mem_size(void);
+
+ mips_memory_upper = tx4927_get_mem_size() << 20;
+ mips_memory_upper += KSEG0;
+ mips_pci_io_base = TX4927_PCIIO;
+ mips_pci_io_size = TX4927_PCIIO_SIZE;
+ mips_pci_mem_base = TX4927_PCIMEM;
+ mips_pci_mem_size = TX4927_PCIMEM_SIZE;
+
+ if (!called) {
+ printk
+ ("%s PCIC -- DID:%04x VID:%04x RID:%02x Arbiter:%s\n",
+ toshiba_name,
+ (unsigned short) (tx4927_pcicptr->pciid >> 16),
+ (unsigned short) (tx4927_pcicptr->pciid & 0xffff),
+ (unsigned short) (tx4927_pcicptr->pciccrev & 0xff),
+ (!(tx4927_ccfgptr->
+ ccfg & TX4927_CCFG_PCIXARB)) ? "External" :
+ "Internal");
+ called = 1;
+ }
+ printk("%s PCIC --%s PCICLK:", toshiba_name,
+ (tx4927_ccfgptr->ccfg & TX4927_CCFG_PCI66) ? " PCI66" : "");
+ if (tx4927_ccfgptr->pcfg & TX4927_PCFG_PCICLKEN_ALL) {
+ int pciclk = 0;
+ if (mips_machtype == MACH_TOSHIBA_RBTX4937)
+ switch ((unsigned long) tx4927_ccfgptr->
+ ccfg & TX4937_CCFG_PCIDIVMODE_MASK) {
+ case TX4937_CCFG_PCIDIVMODE_4:
+ pciclk = tx4927_cpu_clock / 4;
+ break;
+ case TX4937_CCFG_PCIDIVMODE_4_5:
+ pciclk = tx4927_cpu_clock * 2 / 9;
+ break;
+ case TX4937_CCFG_PCIDIVMODE_5:
+ pciclk = tx4927_cpu_clock / 5;
+ break;
+ case TX4937_CCFG_PCIDIVMODE_5_5:
+ pciclk = tx4927_cpu_clock * 2 / 11;
+ break;
+ case TX4937_CCFG_PCIDIVMODE_8:
+ pciclk = tx4927_cpu_clock / 8;
+ break;
+ case TX4937_CCFG_PCIDIVMODE_9:
+ pciclk = tx4927_cpu_clock / 9;
+ break;
+ case TX4937_CCFG_PCIDIVMODE_10:
+ pciclk = tx4927_cpu_clock / 10;
+ break;
+ case TX4937_CCFG_PCIDIVMODE_11:
+ pciclk = tx4927_cpu_clock / 11;
+ break;
+ }
+
+ else
+ switch ((unsigned long) tx4927_ccfgptr->
+ ccfg & TX4927_CCFG_PCIDIVMODE_MASK) {
+ case TX4927_CCFG_PCIDIVMODE_2_5:
+ pciclk = tx4927_cpu_clock * 2 / 5;
+ break;
+ case TX4927_CCFG_PCIDIVMODE_3:
+ pciclk = tx4927_cpu_clock / 3;
+ break;
+ case TX4927_CCFG_PCIDIVMODE_5:
+ pciclk = tx4927_cpu_clock / 5;
+ break;
+ case TX4927_CCFG_PCIDIVMODE_6:
+ pciclk = tx4927_cpu_clock / 6;
+ break;
+ }
+
+ printk("Internal(%dMHz)", pciclk / 1000000);
+ } else
+ printk("External");
+ printk("\n");
+
+ /* GB->PCI mappings */
+ tx4927_pcicptr->g2piomask = (mips_pci_io_size - 1) >> 4;
+ tx4927_pcicptr->g2piogbase = mips_pci_io_base |
+#ifdef __BIG_ENDIAN
+ TX4927_PCIC_G2PIOGBASE_ECHG
+#else
+ TX4927_PCIC_G2PIOGBASE_BSDIS
+#endif
+ ;
+
+ tx4927_pcicptr->g2piopbase = 0;
+
+ tx4927_pcicptr->g2pmmask[0] = (mips_pci_mem_size - 1) >> 4;
+ tx4927_pcicptr->g2pmgbase[0] = mips_pci_mem_base |
+#ifdef __BIG_ENDIAN
+ TX4927_PCIC_G2PMnGBASE_ECHG
+#else
+ TX4927_PCIC_G2PMnGBASE_BSDIS
+#endif
+ ;
+ tx4927_pcicptr->g2pmpbase[0] = mips_pci_mem_base;
+
+ tx4927_pcicptr->g2pmmask[1] = 0;
+ tx4927_pcicptr->g2pmgbase[1] = 0;
+ tx4927_pcicptr->g2pmpbase[1] = 0;
+ tx4927_pcicptr->g2pmmask[2] = 0;
+ tx4927_pcicptr->g2pmgbase[2] = 0;
+ tx4927_pcicptr->g2pmpbase[2] = 0;
+
+
+ /* PCI->GB mappings (I/O 256B) */
+ tx4927_pcicptr->p2giopbase = 0; /* 256B */
+
+ /* PCI->GB mappings (MEM 512MB) M0 gets all of memory */
+ tx4927_pcicptr->p2gm0plbase = 0;
+ tx4927_pcicptr->p2gm0pubase = 0;
+ tx4927_pcicptr->p2gmgbase[0] = 0 | TX4927_PCIC_P2GMnGBASE_TMEMEN |
+#ifdef __BIG_ENDIAN
+ TX4927_PCIC_P2GMnGBASE_TECHG
+#else
+ TX4927_PCIC_P2GMnGBASE_TBSDIS
+#endif
+ ;
+
+ /* PCI->GB mappings (MEM 16MB) -not used */
+ tx4927_pcicptr->p2gm1plbase = 0xffffffff;
+ tx4927_pcicptr->p2gm1pubase = 0xffffffff;
+ tx4927_pcicptr->p2gmgbase[1] = 0;
+
+ /* PCI->GB mappings (MEM 1MB) -not used */
+ tx4927_pcicptr->p2gm2pbase = 0xffffffff;
+ tx4927_pcicptr->p2gmgbase[2] = 0;
+
+
+ /* Enable Initiator Memory 0 Space, I/O Space, Config */
+ tx4927_pcicptr->pciccfg &= TX4927_PCIC_PCICCFG_LBWC_MASK;
+ tx4927_pcicptr->pciccfg |=
+ TX4927_PCIC_PCICCFG_IMSE0 | TX4927_PCIC_PCICCFG_IISE |
+ TX4927_PCIC_PCICCFG_ICAE | TX4927_PCIC_PCICCFG_ATR;
+
+
+ /* Do not use MEMMUL, MEMINF: YMFPCI card causes M_ABORT. */
+ tx4927_pcicptr->pcicfg1 = 0;
+
+ if (tx4927_pcic_trdyto >= 0) {
+ tx4927_pcicptr->g2ptocnt &= ~0xff;
+ tx4927_pcicptr->g2ptocnt |= (tx4927_pcic_trdyto & 0xff);
+ }
+
+ /* Clear All Local Bus Status */
+ tx4927_pcicptr->pcicstatus = TX4927_PCIC_PCICSTATUS_ALL;
+ /* Enable All Local Bus Interrupts */
+ tx4927_pcicptr->pcicmask = TX4927_PCIC_PCICSTATUS_ALL;
+ /* Clear All Initiator Status */
+ tx4927_pcicptr->g2pstatus = TX4927_PCIC_G2PSTATUS_ALL;
+ /* Enable All Initiator Interrupts */
+ tx4927_pcicptr->g2pmask = TX4927_PCIC_G2PSTATUS_ALL;
+ /* Clear All PCI Status Error */
+ tx4927_pcicptr->pcistatus =
+ (tx4927_pcicptr->pcistatus & 0x0000ffff) |
+ (TX4927_PCIC_PCISTATUS_ALL << 16);
+ /* Enable All PCI Status Error Interrupts */
+ tx4927_pcicptr->pcimask = TX4927_PCIC_PCISTATUS_ALL;
+
+ /* PCIC Int => IRC IRQ16 */
+ tx4927_pcicptr->pcicfg2 =
+ (tx4927_pcicptr->pcicfg2 & 0xffffff00) | TX4927_IR_PCIC;
+
+ if (!(tx4927_ccfgptr->ccfg & TX4927_CCFG_PCIXARB)) {
+ /* XXX */
+ } else {
+ /* Reset Bus Arbiter */
+ tx4927_pcicptr->pbacfg = TX4927_PCIC_PBACFG_RPBA;
+ /* Enable Bus Arbiter */
+ tx4927_pcicptr->pbacfg = TX4927_PCIC_PBACFG_PBAEN;
+ }
+
+ tx4927_pcicptr->pcistatus = PCI_COMMAND_MASTER |
+ PCI_COMMAND_MEMORY |
+ PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
+}
+#endif /* CONFIG_PCI */
+
+static void __noreturn wait_forever(void)
+{
+ while (1)
+ if (cpu_wait)
+ (*cpu_wait)();
+}
+
+void toshiba_rbtx4927_restart(char *command)
+{
+ printk(KERN_NOTICE "System Rebooting...\n");
+
+ /* enable the s/w reset register */
+ writeb(RBTX4927_SW_RESET_ENABLE_SET, RBTX4927_SW_RESET_ENABLE);
+
+ /* wait for enable to be seen */
+ while ((readb(RBTX4927_SW_RESET_ENABLE) &
+ RBTX4927_SW_RESET_ENABLE_SET) == 0x00);
+
+ /* do a s/w reset */
+ writeb(RBTX4927_SW_RESET_DO_SET, RBTX4927_SW_RESET_DO);
+
+ /* do something passive while waiting for reset */
+ local_irq_disable();
+ wait_forever();
+ /* no return */
+}
+
+void toshiba_rbtx4927_halt(void)
+{
+ printk(KERN_NOTICE "System Halted\n");
+ local_irq_disable();
+ wait_forever();
+ /* no return */
+}
+
+void toshiba_rbtx4927_power_off(void)
+{
+ toshiba_rbtx4927_halt();
+ /* no return */
+}
+
+void __init plat_mem_setup(void)
+{
+ int i;
+ u32 cp0_config;
+ char *argptr;
+
+ printk("CPU is %s\n", toshiba_name);
+
+ /* f/w leaves this on at startup */
+ clear_c0_status(ST0_ERL);
+
+ /* enable caches -- HCP5 does this, pmon does not */
+ cp0_config = read_c0_config();
+ cp0_config = cp0_config & ~(TX49_CONF_IC | TX49_CONF_DC);
+ write_c0_config(cp0_config);
+
+ set_io_port_base(KSEG1 + TBTX4927_ISA_IO_OFFSET);
+
+ ioport_resource.end = 0xffffffff;
+ iomem_resource.end = 0xffffffff;
+
+ _machine_restart = toshiba_rbtx4927_restart;
+ _machine_halt = toshiba_rbtx4927_halt;
+ pm_power_off = toshiba_rbtx4927_power_off;
+
+ for (i = 0; i < TX4927_NR_TMR; i++)
+ txx9_tmr_init(TX4927_TMR_REG(0) & 0xfffffffffULL);
+
+#ifdef CONFIG_PCI
+
+ /* PCIC */
+ /*
+ * ASSUMPTION: PCIDIVMODE is configured for PCI 33MHz or 66MHz.
+ *
+ * For TX4927:
+ * PCIDIVMODE[12:11]'s initial value is given by S9[4:3] (ON:0, OFF:1).
+ * CPU 166MHz: PCI 66MHz : PCIDIVMODE: 00 (1/2.5)
+ * CPU 200MHz: PCI 66MHz : PCIDIVMODE: 01 (1/3)
+ * CPU 166MHz: PCI 33MHz : PCIDIVMODE: 10 (1/5)
+ * CPU 200MHz: PCI 33MHz : PCIDIVMODE: 11 (1/6)
+ * i.e. S9[3]: ON (83MHz), OFF (100MHz)
+ *
+ * For TX4937:
+ * PCIDIVMODE[12:11]'s initial value is given by S1[5:4] (ON:0, OFF:1)
+ * PCIDIVMODE[10] is 0.
+ * CPU 266MHz: PCI 33MHz : PCIDIVMODE: 000 (1/8)
+ * CPU 266MHz: PCI 66MHz : PCIDIVMODE: 001 (1/4)
+ * CPU 300MHz: PCI 33MHz : PCIDIVMODE: 010 (1/9)
+ * CPU 300MHz: PCI 66MHz : PCIDIVMODE: 011 (1/4.5)
+ * CPU 333MHz: PCI 33MHz : PCIDIVMODE: 100 (1/10)
+ * CPU 333MHz: PCI 66MHz : PCIDIVMODE: 101 (1/5)
+ *
+ */
+ if (mips_machtype == MACH_TOSHIBA_RBTX4937)
+ switch ((unsigned long)tx4927_ccfgptr->
+ ccfg & TX4937_CCFG_PCIDIVMODE_MASK) {
+ case TX4937_CCFG_PCIDIVMODE_8:
+ case TX4937_CCFG_PCIDIVMODE_4:
+ tx4927_cpu_clock = 266666666; /* 266MHz */
+ break;
+ case TX4937_CCFG_PCIDIVMODE_9:
+ case TX4937_CCFG_PCIDIVMODE_4_5:
+ tx4927_cpu_clock = 300000000; /* 300MHz */
+ break;
+ default:
+ tx4927_cpu_clock = 333333333; /* 333MHz */
+ }
+ else
+ switch ((unsigned long)tx4927_ccfgptr->
+ ccfg & TX4927_CCFG_PCIDIVMODE_MASK) {
+ case TX4927_CCFG_PCIDIVMODE_2_5:
+ case TX4927_CCFG_PCIDIVMODE_5:
+ tx4927_cpu_clock = 166666666; /* 166MHz */
+ break;
+ default:
+ tx4927_cpu_clock = 200000000; /* 200MHz */
+ }
+
+ /* CCFG */
+ /* do reset on watchdog */
+ tx4927_ccfgptr->ccfg |= TX4927_CCFG_WR;
+ /* enable Timeout BusError */
+ if (tx4927_ccfg_toeon)
+ tx4927_ccfgptr->ccfg |= TX4927_CCFG_TOE;
+
+ tx4927_pci_setup();
+ if (tx4927_using_backplane == 1)
+ printk("backplane board IS installed\n");
+ else
+ printk("No Backplane \n");
+
+ /* this is on ISA bus behind PCI bus, so need PCI up first */
+#ifdef CONFIG_TOSHIBA_FPCIB0
+ if (tx4927_using_backplane) {
+ smsc_fdc37m81x_init(0x3f0);
+ smsc_fdc37m81x_config_beg();
+ smsc_fdc37m81x_config_set(SMSC_FDC37M81X_DNUM,
+ SMSC_FDC37M81X_KBD);
+ smsc_fdc37m81x_config_set(SMSC_FDC37M81X_INT, 1);
+ smsc_fdc37m81x_config_set(SMSC_FDC37M81X_INT2, 12);
+ smsc_fdc37m81x_config_set(SMSC_FDC37M81X_ACTIVE,
+ 1);
+ smsc_fdc37m81x_config_end();
+ }
+#endif
+#endif /* CONFIG_PCI */
+
+#ifdef CONFIG_SERIAL_TXX9
+ {
+ extern int early_serial_txx9_setup(struct uart_port *port);
+ struct uart_port req;
+ for(i = 0; i < 2; i++) {
+ memset(&req, 0, sizeof(req));
+ req.line = i;
+ req.iotype = UPIO_MEM;
+ req.membase = (char *)(0xff1ff300 + i * 0x100);
+ req.mapbase = 0xff1ff300 + i * 0x100;
+ req.irq = TX4927_IRQ_PIC_BEG + 8 + i;
+ req.flags |= UPF_BUGGY_UART /*HAVE_CTS_LINE*/;
+ req.uartclk = 50000000;
+ early_serial_txx9_setup(&req);
+ }
+ }
+#ifdef CONFIG_SERIAL_TXX9_CONSOLE
+ argptr = prom_getcmdline();
+ if (strstr(argptr, "console=") == NULL) {
+ strcat(argptr, " console=ttyS0,38400");
+ }
+#endif
+#endif
+
+#ifdef CONFIG_ROOT_NFS
+ argptr = prom_getcmdline();
+ if (strstr(argptr, "root=") == NULL) {
+ strcat(argptr, " root=/dev/nfs rw");
+ }
+#endif
+
+#ifdef CONFIG_IP_PNP
+ argptr = prom_getcmdline();
+ if (strstr(argptr, "ip=") == NULL) {
+ strcat(argptr, " ip=any");
+ }
+#endif
+}
+
+void __init plat_time_init(void)
+{
+ mips_hpt_frequency = tx4927_cpu_clock / 2;
+ if (tx4927_ccfgptr->ccfg & TX4927_CCFG_TINTDIS)
+ txx9_clockevent_init(TX4927_TMR_REG(0) & 0xfffffffffULL,
+ TXX9_IRQ_BASE + 17,
+ 50000000);
+}
+
+static int __init toshiba_rbtx4927_rtc_init(void)
+{
+ static struct resource __initdata res = {
+ .start = 0x1c010000,
+ .end = 0x1c010000 + 0x800 - 1,
+ .flags = IORESOURCE_MEM,
+ };
+ struct platform_device *dev =
+ platform_device_register_simple("rtc-ds1742", -1, &res, 1);
+ return IS_ERR(dev) ? PTR_ERR(dev) : 0;
+}
+device_initcall(toshiba_rbtx4927_rtc_init);
+
+static int __init rbtx4927_ne_init(void)
+{
+ static struct resource __initdata res[] = {
+ {
+ .start = RBTX4927_RTL_8019_BASE,
+ .end = RBTX4927_RTL_8019_BASE + 0x20 - 1,
+ .flags = IORESOURCE_IO,
+ }, {
+ .start = RBTX4927_RTL_8019_IRQ,
+ .flags = IORESOURCE_IRQ,
+ }
+ };
+ struct platform_device *dev =
+ platform_device_register_simple("ne", -1,
+ res, ARRAY_SIZE(res));
+ return IS_ERR(dev) ? PTR_ERR(dev) : 0;
+}
+device_initcall(rbtx4927_ne_init);
+
+/* Watchdog support */
+
+static int __init txx9_wdt_init(unsigned long base)
+{
+ struct resource res = {
+ .start = base,
+ .end = base + 0x100 - 1,
+ .flags = IORESOURCE_MEM,
+ };
+ struct platform_device *dev =
+ platform_device_register_simple("txx9wdt", -1, &res, 1);
+ return IS_ERR(dev) ? PTR_ERR(dev) : 0;
+}
+
+static int __init rbtx4927_wdt_init(void)
+{
+ return txx9_wdt_init(TX4927_TMR_REG(2) & 0xfffffffffULL);
+}
+device_initcall(rbtx4927_wdt_init);
+
+/* Minimum CLK support */
+
+struct clk *clk_get(struct device *dev, const char *id)
+{
+ if (!strcmp(id, "imbus_clk"))
+ return (struct clk *)50000000;
+ return ERR_PTR(-ENOENT);
+}
+EXPORT_SYMBOL(clk_get);
+
+int clk_enable(struct clk *clk)
+{
+ return 0;
+}
+EXPORT_SYMBOL(clk_enable);
+
+void clk_disable(struct clk *clk)
+{
+}
+EXPORT_SYMBOL(clk_disable);
+
+unsigned long clk_get_rate(struct clk *clk)
+{
+ return (unsigned long)clk;
+}
+EXPORT_SYMBOL(clk_get_rate);
+
+void clk_put(struct clk *clk)
+{
+}
+EXPORT_SYMBOL(clk_put);
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