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* OMAP3/4 clock: split into per-chip family filesPaul Walmsley2010-02-2417-332/+450
| | | | | | | | | | | | | | | | | | | | | | | | | | | clock34xx_data.c now contains data for the OMAP34xx family, the OMAP36xx family, and the OMAP3517 family, so rename it to clock3xxx_data.c. Rename clock34xx.c to clock3xxx.c, and move the chip family-specific clock functions to clock34xx.c, clock36xx.c, or clock3517.c, as appropriate. So now "clock3xxx.*" refers to the OMAP3 superset. The main goal here is to prepare to compile chip family-specific clock functions only for kernel builds that target that chip family. To get to that point, we also need to add CONFIG_SOC_* options for those other chip families; that will be done in future patches, planned for 2.6.35. OMAP4 is also affected by this. It duplicated the OMAP3 non-CORE DPLL clkops structure. The OMAP4 variant of this clkops structure has been removed, and since there was nothing else currently in clock44xx.c, it too has been removed -- it can always be added back later when there is some content for it. (The OMAP4 clock autogeneration scripts have been updated accordingly.) Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Benoît Cousson <b-cousson@ti.com> Cc: Rajendra Nayak <rnayak@ti.com> Cc: Ranjith Lohithakshan <ranjithl@ti.com> Cc: Tony Lindgren <tony@atomide.com>
* OMAP clock: drop .id field; ensure each clock has a unique namePaul Walmsley2010-02-245-121/+61
| | | | | | | | After the clkdev conversion, the struct clk.id field became superfluous, so, drop it. Bring the clock names closer to the TRMs and ensure they are unique for debugfs. Signed-off-by: Paul Walmsley <paul@pwsan.com>
* OMAP clock: compress clock flags down to a u8Paul Walmsley2010-02-241-15/+9
| | | | | | | | There are now only eight OMAP clock flags, so renumber the flags to fit in a u8 and shrink the size of struct clk.flags from a u32 to a u8. The intention is to save memory. Signed-off-by: Paul Walmsley <paul@pwsan.com>
* OMAP2 clock: drop CONFIG_PARTICIPANT clock flagPaul Walmsley2010-02-243-36/+12
| | | | | | | | | | | | | | | | | It turns out that the only purpose of the CONFIG_PARTICIPANT clock flag is to prevent omap2_clk_set_rate() and omap2_clk_set_parent() from being executed on clocks with that flag set. The rate-changing component can be more directly accomplished by dropping the .set_rate and .round_rate function pointers from those CONFIG_PARTICIPANT struct clks. As far as the parent-changing component is concerned, it turns out that none of the CONFIG_PARTICIPANT clocks have multiple parent choices, so all that is necessary is for omap2_clk_set_parent() to bail out early if the new parent is equal to the old parent. Implement this change and get rid of the flag, which has always had a confusing name (it appears to be a Kconfig option, falsely). Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Richard Woodruff <r-woodruff2@ti.com>
* OMAP2xxx clock: drop DELAYED_APP flag from non-clksel clocksPaul Walmsley2010-02-241-4/+3
| | | | | | | | | The DELAYED_APP flag is effective only with clksel clocks, so drop it from clocks that are not rate-changeable or that use non-clksel rate changing code (e.g., virt_prcm_set). Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Richard Woodruff <r-woodruff2@ti.com>
* OMAP2xxx clock: GFX functional clock rates are not independently changeablePaul Walmsley2010-02-241-1/+2
| | | | | | | | | | According to the OMAP242x TRM Rev X Figure 5-15 "Clock Output Control - Functional Clocks 2", the GFX functional clocks should be marked both DELAYED_APP and CONFIG_PARTICIPANT, meaning that their rates must be reprogrammed as part of a larger OPP set change. Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Richard Woodruff <r-woodruff2@ti.com>
* OMAP4 clock: drop the CLOCK_IN_OMAP4430 clock flagPaul Walmsley2010-02-242-115/+13
| | | | | | | | | | | The CLOCK_IN_OMAP4430 clock flag is not currently needed in the OMAP4 ES1 clock tree, and platform discrimination via clock flags is deprecated in favor of the clkdev mechanism, so, drop it. (The OMAP4 clock tree autogeneration script has been updated accordingly.) Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Benoît Cousson <b-cousson@ti.com> Cc: Rajendra Nayak <rnayak@ti.com>
* OMAP2/3/4 clock: fix DPLL multiplier value errors; also copyrights, ↵Paul Walmsley2010-02-247-26/+67
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | includes, documentation The maximum DPLL multiplier (M) values for OMAP2xxx and OMAP3xxx are one increment higher than they should be. See for example the OMAP242x TRM Rev X Section 5.10.6 "Clock Generator Registers" and the OMAP36xx TRM Rev C Table 3-202 "CM_CLKSEL1_PLL". Programming a 0 into the DPLL's M register bitfield is valid for OMAP2/3 and indicates that the DPLL should enter MN-bypass mode. Also, increase the minimum multiplier (M) value for the DPLL rate rounding code from 1 to 2, to ensure that it does not inadvertently put the DPLL into bypass. Note that the register documentation in the OMAP2xxx and OMAP3xxx TRMs does not make clear that the actual DPLL divider value (the "N") is the content of the appropriate register bitfield for the N value, _plus one_. (In other words, an N register bitfield of 0 indicates a DPLL divider value of 1.) This is only clearly documented in the OMAP4430 TRM, in, for example, OMAP4430 TRM Rev A Table 3-1167 "CM_CLKSEL_DPLL_USB". While here, update copyrights, add kerneldoc for struct dpll_data, drop the unused struct dpll_data.max_tolerance field, remove some unnecessary #includes in DPLL-related code, and replace the #include of <linux/module.h> with <linux/list.h>, which is what was really needed. The OMAP4 clock autogenerator script has been updated accordingly. Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Benoît Cousson <b-cousson@ti.com> Cc: Rajendra Nayak <rnayak@ti.com>
* OMAP3 clock: add support for 192Mhz DPLL4M2 outputVishwanath BS2010-02-244-8/+65
| | | | | | | | | | | | | | | In 3630, DPLL4M2 output can be 96MHz or 192MHz (for SGX to run at 192). This patch has changes to support this feature. 96MHz clock is generated by dividing 192Mhz clock by 2 using CM_CLKSEL_CORE register. SGX can select Core Clock, 192MHz clock or CM_96M_FCLK as it's functional clock. In summary changes done are: 1. Added a feature called omap3_has_192mhz_clk and enabled for 3630 2. Added a new clock node called omap_192m_alwon_ck 3. Made omap_96m_alwon_fck to derive its clock from omap_192m_alwon_ck Signed-off-by: Vishwanath BS <Vishwanath.bs@ti.com> [paul@pwsan.com: fixed whitespace] Signed-off-by: Paul Walmsley <paul@pwsan.com>
* OMAP3 clock: Introduce 3630 DPLL4 HSDivider changesVishwanath BS2010-02-243-7/+149
| | | | | | | | | | | | Divider (M2, M3, M4, M5 and M6) field width has been increased by 1 bit in 3630. This patch has changes to accommodate this in CM dynamically based on chip version. Basically new clock nodes have been added for 3630 DPLL4 M2,M3,M4,M5 and M6 and value of these nodes are used if cpu type is 3630. Signed-off-by: Vishwanath BS <vishwanath.bs@ti.com> [paul@pwsan.com: updated to apply on 2.6.34 queue; comments added] Signed-off-by: Paul Walmsley <paul@pwsan.com>
* OMAP3 clock: introduce DPLL4 JtypeRichard Woodruff2010-02-246-5/+109
| | | | | | | | | | | | | | | | DPLL4 for 3630 introduces a changed block called j type dpll, requiring special divisor bits and additional reg fields. To allow for silicons to use this, this is introduced as a flag and is enabled for 3630 silicon. OMAP4 also has j type dpll for usb. Tested with 3630 ZOOM3 and OMAP3430 ZOOM2 Signed-off-by: Richard Woodruff <r-woodruff2@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Vishwanath BS <Vishwanath.bs@ti.com> [paul@pwsan.com: added some comments; updated copyrights and credits; fixed some style issues] Signed-off-by: Paul Walmsley <paul@pwsan.com>
* ARM: OMAP4 clock domain: Add check for avoiding dependency related update.Abhijit Pagare2010-02-241-6/+24
| | | | | | | | | A check is added for avoiding the sleep/wakeup dependency updates for OMAP4 as the structures for the dependencies are currently absent. Signed-off-by: Abhijit Pagare <abhijitpagare@ti.com> [paul@pwsan.com: added warnings, explanatory comment, copyright update] Signed-off-by: Paul Walmsley <paul@pwsan.com>
* OMAP3630: Clock: Workaround for DPLL HS divider limitationMike Turquette2010-02-243-0/+65
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch implements a workaround for the DPLL HS divider limitation in OMAP3630 as given by Errata ID: i556. Errata: When PWRDN bit is set, it resets the internal HSDIVIDER divide-by value (Mx). The reset value gets loaded instead of the previous value. The following HSDIVIDERs exhibit above behavior: . DPLL4 : M6 / M5 / M4 / M3 / M2 (CM_CLKEN_PLL[31:26] register bits) . DPLL3 : M3 (CM_CLKEN_PLL[12] register bit). Work Around: It is mandatory to apply the following sequence to ensure the write value will be loaded in DPLL HSDIVIDER FSM: The global sequence when using PWRDN bit is the following: . Disable Mx HSDIVIDER clock output related functional clock enable bits (in CM_FCLKEN_xxx / CM_ICLKEN_xxx) . Enable PWRDN bit of HSDIVIDER . Disable PWRDN bit of HSDIVIDER . Read current HSDIVIDER register value . Write different value in HSDIVIDER register . Write expected value in HSDIVIDER register . Enable Mx HSDIVIDER clock output related functional clocks (CM_FCLKEN_xxx / CM_ICLKEN_xxx) Signed-off-by: Mike Turquette <mturquette@ti.com> Signed-off-by: Vishwanath BS <vishwanath.bs@ti.com> Signed-off-by: Vijaykumar GN <vijaykumar.gn@ti.com> [paul@pwsan.com: updated patch to apply; made workaround function static; marked as being 36xx-specific] Signed-off-by: Paul Walmsley <paul@pwsan.com>
* OMAP: HWMOD: Add support for early device register into omap device layerThara Gopinath2010-02-242-6/+32
| | | | | | | | | | | | | This patch adds support in omap device layer to register devices as early platform devices. Certain devices needed during system boot up like timers, gpio etc can be registered as early devices. This will allow for them to be probed very early on during system boot up. This patch adds a parameter is_early_device in omap_device_build. Depending on this parameter a call to early_platform_add_devices or platform_register_device is made. Signed-off-by: Thara Gopinath <thara@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
* OMAP3: hwmod: support to specify the offset position of various SYSCONFIG ↵Thara Gopinath2010-02-244-29/+191
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | register bits. In OMAP3 Some modules like Smartreflex do not have the regular sysconfig register.Instead clockactivity bits are part of another register at a different bit position than the usual bit positions 8 and 9. In OMAP4, a new scheme is available due to the new protocol between the PRCM and the IPs. Depending of the scheme, the SYSCONFIG bitfields position will be different. The IP_REVISION register should be at offset 0x00. It should contain a SCHEME field. From this we can determine whether the IP follows legacy scheme or the new scheme. 31:30 SCHEME Used to distinguish between old scheme and current. Read 0x0: Legacy protocol. Read 0x1: New PRCM protocol defined for new OMAP4 IPs For legacy IP 13:12 MIDLEMODE 11:8 CLOCKACTIVITY 6 EMUSOFT 5 EMUFREE 4:3 SIDLEMODE 2 ENAWAKEUP 1 SOFTRESET 0 AUTOIDLE For new OMAP4 IP's, the bit position in SYSCONFIG is (for simple target): 5:4 STANDBYMODE (Ex MIDLEMODE) 3:2 IDLEMODE (Ex SIDLEMODE) 1 FREEEMU (Ex EMUFREE) 0 SOFTRESET Unfortunately In OMAP4 also some IPs will not follow any of these two schemes. This is the case at least for McASP, SmartReflex and some security IPs. This patch introduces a new field sysc_fields in omap_hwmod_sysconfig which can be used by the hwmod structures to specify the offsets for the sysconfig register of the IP.Also two static structures omap_hwmod_sysc_type1 and omap_hwmod_sysc_type2 are defined which can be used directly to populate the sysc_fields if the IP follows legacy or new OMAP4 scheme. If the IP follows none of these two schemes a new omap_hwmod_sysc_fields structure has to be defined and passed as part of omap_hwmod_sysconfig. Signed-off-by: Thara Gopinath <thara@ti.com> Signed-off-by: Benoit Cousson <b-cousson@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
* OMAP3 clock: Remove FreqSel for 3630Vishwanath BS2010-02-241-4/+7
| | | | | | | | | | DPLL_FREQSEL field in CLKEN_PLL register is no longer valid for OMAP3630. So remove references to that. Signed-off-by: Vishwanath BS <vishwanath.bs@ti.com> Cc: Sergei Shtylyov <sshtylyov@mvista.com> [paul@pwsan.com: added comment fix from Sergei Shtylyov] Signed-off-by: Paul Walmsley <paul@pwsan.com>
* OMAP2/3: PRCM: fix misc. compiler warningsKevin Hilman2010-02-241-1/+3
| | | | | | | | - missing return in omap_prcm_get_reset_sources() - potential use of uninitialized variable in omap_prcm_arch_reset() Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
* OMAP3 clock: Check return values for clk_get()Sanjeev Premi2010-02-241-0/+16
| | | | | | | | | | | This patch checks if clk_get() returned success for the clocks used in function omap2_clk_arch_init(). This version incorporates review comments from Kevin Hilman and Paul Walmsley. Signed-off-by: Sanjeev Premi <premi@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
* AM35xx: Add clock support for new modules on AM35xxRanjith Lohithakshan2010-02-244-0/+225
| | | | | | | | | | | | This patch adds clock support for the following AM35xx modules - Ethernet MAC - CAN Controller (HECC) - New MUSB OTG Controller with integrated Phy - Video Processing Front End (VPFE) - Additional UART (UART4) Signed-off-by: Ranjith Lohithakshan <ranjithl@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
* OMAP2/3 clock: Extend find_idlest() to pass back idle state valueRanjith Lohithakshan2010-02-249-23/+52
| | | | | | | | | | | | | | | | Current implementation defines clock idle state indicators based on the cpu information (cpu_is_omap24xx() or cpu_is_omap34xx()) in a system wide manner. This patch extends the find_idlest() function in clkops to pass back the idle state indicator for that clock, thus allowing idle state indicators to be defined on a per clock basis if required. This is specifically needed on AM35xx devices as the new IPSS clocks indicates the idle status (0 is idle, 1 is ready) in a way just opposite to how its handled in OMAP3 (0 is ready, 1 is idle). Signed-off-by: Ranjith Lohithakshan <ranjithl@ti.com> [paul@pwsan.com: updated to apply after commit 98c45457 et seq.] Signed-off-by: Paul Walmsley <paul@pwsan.com>
* OMAP3 PM: Adding counters for power domain logic off and mem off during ↵Thara Gopinath2010-02-243-0/+32
| | | | | | | | | | | | | | | | | | | | | | retention. This patch adds counters to keep track of whether the powerdomain logic or software controllable memory banks are turned off when the power domain enters retention. During power domain retention if logic gets turned off, the scenario is known as Open Switch Retention. Also during retention s/w controllable memory banks of a power domain can be chosen to be kept in retention or off. This patch adds one counter per powerdomain to track the power domain logic state during retention. Number of memory bank state counters added depends on the number of software controllable memory banks of the powerdomain. To view these counters do cat ../debug/pm_debug/count Signed-off-by: Thara Gopinath <thara@ti.com> [paul@pwsan.com: conditional expressions simplified; counter increment code moved to its own function] Signed-off-by: Paul Walmsley <paul@pwsan.com>
* OMAP3 PM: Defining .pwrsts_logic_ret field for core power domain structureThara Gopinath2010-02-241-0/+2
| | | | | | | | | This patch adds the flag .pwrsts_logic_ret info for the core power domain in the associated powerdomain structure. This flag specifies the states core domain logic can hit in event of the domain entering retention. Signed-off-by: Thara Gopinath <thara@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
* OMAP2/3 PM: Adding powerdomain APIs for reading the next logic and mem stateThara Gopinath2010-02-242-0/+75
| | | | | | | | | | | This patch adds APIs pwrdm_read_logic_retst and pwrdm_read_mem_retst for reading the next programmed logic and memory state a powerdomain is to hit in event of the next power domain state being retention. These are needed for OSWR support. Signed-off-by: Thara Gopinath <thara@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
* OMAP3: Clock: Added IDLEST definitions for SGXTero Kristo2010-02-241-0/+4
| | | | | | | | Added definitions for OMAP3430ES2_ST_SGX_SHIFT and OMAP3430ES2_ST_SGX_MASK as these were missing. Signed-off-by: Tero Kristo <tero.kristo@nokia.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
* OMAP3: clock: use std _MASK suffix for CM_FCLKEN_IVA2 definesKevin Hilman2010-02-242-2/+2
| | | | | | | | Add _MASK suffix to CM_FCLKEN_IVA2 bitfieds to conform with the rest of the usage in cm-regbits-34xx.h of using _SHIFT and _MASK suffixes. Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
* OMAP: omap_device: when 'called from invalid state', print stateKevin Hilman2010-02-241-6/+6
| | | | | | | | | | | | | | The omap_device_[enable|idle|shutdown] functions print a warning when called from an invalid state. Print the invalid state in the warning messages. This also uses __func__ to get the function name. Also, move the entire print string onto a single line to facilitate grepping or error messages. Recent discussions on LKML show strong preference for grep-able code vs. strict 80 column limit. Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
* OMAP: omap_device: add omap_device_is_valid()Kevin Hilman2010-02-242-0/+18
| | | | | | | | | | | | | | | | | | The omap_device struct contains a 'struct platform_device'. Normally, converting a platform_device pointer to an omap_device pointer consists of simply doing a container_of(), as is done currently by the to_omap_device() macro. However, if this is attempted when using platform_device that has not been created as part of the omap_device creation, the container_of() will point to a memory location before the platform_device pointer which will contain random data. Therefore, we need a way to detect valid omap_device pointers. This patch solves this by using the simple magic number approach. Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
* Merge branch 'omap-fixes-for-linus' into omap-for-linusTony Lindgren2010-02-17219-1393/+2611
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| * omap: Remove DEBUG_FS dependency for mux name checkingRanjith Lohithakshan2010-02-171-7/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The check for a valid mux name should be performed regardless of whether DEBUG_FS is enabled or not. Otherwise without DEBUG_FS, we get: Unable to handle kernel NULL pointer dereference at virtual address 00000000 pgd = c0004000 [00000000] *pgd=00000000 Internal error: Oops: 5 [#1] last sysfs file: Modules linked in: CPU: 0 Not tainted (2.6.33-rc8 #10) PC is at strcmp+0x18/0x40 LR is at omap_mux_init_signal+0x68/0x14c ... This fixes the issue currently seen with boards not booting up if DEBUG_FS is not enabled in defconfig. Note that the earlier ifndef + ifdef now becomes simpler ifdef else: If CONFIG_OMAP_MUX is selected, we use pin names. If it's not selected, we only want the GPIO to mux register mapping. Signed-off-by: Ranjith Lohithakshan <ranjithl@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| * Linux 2.6.33-rc8v2.6.33-rc8Linus Torvalds2010-02-121-1/+1
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| * Merge branch 'fix/hda' of ↵Linus Torvalds2010-02-121-6/+3
| |\ | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound-2.6 * 'fix/hda' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound-2.6: ALSA: hda - use WARN_ON_ONCE() for zero-division detection
| | * ALSA: hda - use WARN_ON_ONCE() for zero-division detectionTakashi Iwai2010-02-121-6/+3
| | | | | | | | | | | | | | | | | | | | | | | | Replace the zero-division warning message with WARN_ON_ONCE() per the advice by Linus. This shouldn't happen, but if it happens, it's possible that the bug happens often due to buggy IRQs. Signed-off-by: Takashi Iwai <tiwai@suse.de>
| * | Merge branch 'for-linus' of ↵Linus Torvalds2010-02-128-142/+332
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/anholt/drm-intel * 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/anholt/drm-intel: drm/i915: hold ref on flip object until it completes drm/i915: Fix crash while aborting hibernation drm/i915: Correctly return -ENOMEM on allocation failure in cmdbuf ioctls. drm/i915: fix pipe source image setting in flip command drm/i915: fix flip done interrupt on Ironlake drm/i915: untangle page flip completion drm/i915: handle FBC and self-refresh better drm/i915: Increase fb alignment to 64k drm/i915: Update write_domains on active list after flush. drm/i915: Rework DPLL calculation parameters for Ironlake
| | * | drm/i915: hold ref on flip object until it completesJesse Barnes2010-02-101-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This will prevent things from falling over if the user frees the flip buffer before we complete the flip, since we'll hold an internal reference. Reported-by: Kristian Høgsberg <krh@bitplanet.net> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Eric Anholt <eric@anholt.net>
| | * | drm/i915: Fix crash while aborting hibernationRafael J. Wysocki2010-02-101-67/+101
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit cbda12d77ea590082edb6d30bd342a67ebc459e0 (drm/i915: implement new pm ops for i915) introduced the problem that if s2disk hibernation is aborted, the system will crash, because i915_pm_freeze() does nothing, while it should at least reverse some operations carried out by i915_suspend(). Fix this issue by splitting the i915 suspend into a freeze part a suspend part, where the latter is not executed before creating a hibernation image, and the i915 resume into a "low-level" resume part and a thaw part, where the former is not executed after the image has been created. Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl> Tested-by: Alan Jenkins <alan-jenkins@tuffmail.co.uk> Signed-off-by: Eric Anholt <eric@anholt.net>
| | * | drm/i915: Correctly return -ENOMEM on allocation failure in cmdbuf ioctls.Owain Ainsworth2010-02-102-2/+6
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Owain G. Ainsworth <oga@openbsd.org> Signed-off-by: Eric Anholt <eric@anholt.net>
| | * | drm/i915: fix pipe source image setting in flip commandZhenyu Wang2010-02-101-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The MI_DISPLAY_FLIP command needs to be set the same pipe source image like in pipe source register, e.g source image size minus one. This fixes screen corrupt issue on Ironlake. Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
| | * | drm/i915: fix flip done interrupt on IronlakeZhenyu Wang2010-02-101-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On Ironlake plane flip interrupt means flip done event already, the behavior is not like old chips, and perform like other usual interrupt. So only need to handle flip done event when receiving that interrupt. Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
| | * | drm/i915: untangle page flip completionJesse Barnes2010-02-101-7/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When a new page flip is requested, we need to both queue an unpin for the current framebuffer, and also increment the flip pending count on the newly submitted buffer. At flip finish time, we need to unpin the old fb and decrement the flip pending count on the new buffer. The old code was conflating the two, and led to hangs when new direct rendered apps were started, replacing the existing frame buffer. This patch splits out the buffers and prevents the hangs. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Kristian Høgsberg <krh@bitplanet.net> Signed-off-by: Eric Anholt <eric@anholt.net>
| | * | drm/i915: handle FBC and self-refresh betterJesse Barnes2010-02-102-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On 945, we need to avoid entering self-refresh if the compressor is busy, or we may cause display FIFO underruns leading to ugly flicker. Fixes fdo bug #24314, kernel bug #15043. Tested-by: Alexander Lam <lambchop468@gmail.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Tested-by: Julien Cristau <jcristau@debian.org> (fd.o #25371) Cc: stable@kernel.org Signed-off-by: Eric Anholt <eric@anholt.net>
| | * | drm/i915: Increase fb alignment to 64kChris Wilson2010-02-101-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | An untiled framebuffer must be aligned to 64k. This is normally handled by intel_pin_and_fence_fb_obj(), but the intelfb_create() likes to be different and do the pinning itself. However, it aligns the buffer object incorrectly for pre-i965 chipsets causing a PGTBL_ERR when it is installed onto the output. Fixes: KMS error message while initializing modesetting - render error detected: EIR: 0x10 [i915] http://bugs.freedesktop.org/show_bug.cgi?id=22936 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: stable@kernel.org Signed-off-by: Eric Anholt <eric@anholt.net>
| | * | drm/i915: Update write_domains on active list after flush.Daniel Vetter2010-02-102-4/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before changing the status of a buffer with a pending write we will await upon a new flush for that buffer. So we can take advantage of any flushes posted whilst the buffer is active and pending processing by the GPU, by clearing its write_domain and updating its last_rendering_seqno -- thus saving a potential flush in deep queues and improves flushing behaviour upon eviction for both GTT space and fences. In order to reduce the time spent searching the active list for matching write_domains, we move those to a separate list whose elements are the buffers belong to the active/flushing list with pending writes. Orignal patch by Chris Wilson <chris@chris-wilson.co.uk>, forward-ported by me. In addition to better performance, this also fixes a real bug. Before this changes, i915_gem_evict_everything didn't work as advertised. When the gpu was actually busy and processing request, the flush and subsequent wait would not move active and dirty buffers to the inactive list, but just to the flushing list. Which triggered the BUG_ON at the end of this function. With the more tight dirty buffer tracking, all currently busy and dirty buffers get moved to the inactive list by one i915_gem_flush operation. I've left the BUG_ON I've used to prove this in there. References: Bug 25911 - 2.10.0 causes kernel oops and system hangs http://bugs.freedesktop.org/show_bug.cgi?id=25911 Bug 26101 - [i915] xf86-video-intel 2.10.0 (and git) triggers kernel oops within seconds after login http://bugs.freedesktop.org/show_bug.cgi?id=26101 Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Tested-by: Adam Lantos <hege@playma.org> Cc: stable@kernel.org Signed-off-by: Eric Anholt <eric@anholt.net>
| | * | drm/i915: Rework DPLL calculation parameters for IronlakeZhenyu Wang2010-02-101-50/+167
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Got Ironlake DPLL parameter table, which reflects the hardware optimized values. So this one trys to list DPLL parameters for different output types, should potential fix clock issue seen on new Arrandale CPUs. This fixes DPLL setting failure on one 1920x1080 dual channel LVDS for Ironlake. Test has also been made on LVDS panels with smaller size and CRT/HDMI/DP ports for different monitors on their all supported modes. Update: - Change name of double LVDS to dual LVDS. - Fix SSC 120M reference clock to use the right range. Cc: CSJ <changsijay@gmail.com> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
| * | | parisc: fix tracing of signalsKyle McMartin2010-02-121-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Mike Frysinger pointed out that calling tracehook_signal_handler with stepping=0 missed testing the thread flags, resulting in not calling ptrace_notify. Fix this by testing if we're single stepping or branch stepping and setting the flag accordingly. Tested, seems to work. Reported-by: Mike Frysinger <vapier@gentoo.org> Signed-off-by: Kyle McMartin <kyle@mcmartin.ca> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
| * | | Merge branch 'fix/hda' of ↵Linus Torvalds2010-02-121-0/+6
| |\ \ \ | | | |/ | | |/| | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound-2.6 * 'fix/hda' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound-2.6: ALSA: hda-intel: Avoid divide by zero crash
| | * | ALSA: hda-intel: Avoid divide by zero crashJody Bruchon2010-02-091-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On my AMD780V chipset, hda_intel.c can crash the kernel with a divide by zero for as-yet unknown reasons. A simple check for zero prevents it, though the problem that causes it remains. Since the workaround is harmless and won't affect anyone except victims of this bug, it should be safe; moreover, because this crash can be triggered by a user-mode application, there are denial of service implications on the systems affected by the bug without the patch. Signed-off-by: Jody Bruchon <jody@nctritech.com> Cc: <stable@kernel.org> Signed-off-by: Takashi Iwai <tiwai@suse.de>
| * | | Merge branch 'for-linus' of ↵Linus Torvalds2010-02-122-3/+3
| |\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/lrg/voltage-2.6 * 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/lrg/voltage-2.6: regulator/lp3971: vol_map out of bounds in lp3971_{ldo,dcdc}_set_voltage() regulator: Fix display of null constraints for regulators
| | * | | regulator/lp3971: vol_map out of bounds in lp3971_{ldo,dcdc}_set_voltage()Roel Kluin2010-02-121-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | After `for (val = LDO_VOL_MIN_IDX; val <= LDO_VOL_MAX_IDX; val++)', if no break occurs, val reaches LDO_VOL_MIN_IDX + 1, which is out of bounds for ldo45_voltage_map[] and ldo123_voltage_map[]. Similarly BUCK_TARGET_VOL_MAX_IDX + 1 is out of bounds for buck_voltage_map[]. Signed-off-by: Roel Kluin <roel.kluin@gmail.com> Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Signed-off-by: Liam Girdwood <lrg@slimlogic.co.uk>
| | * | | regulator: Fix display of null constraints for regulatorsMark Brown2010-02-121-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If the regulator constraints are empty and there is no voltage reported then nothing will be added to the text displayed for the constraints, leading to random stack data being printed. This is unlikely to happen for practical regulators since most will at least report a voltage but should still be fixed. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Cc: stable@kernel.org Signed-off-by: Liam Girdwood <lrg@slimlogic.co.uk>
| * | | | Merge git://git.kernel.org/pub/scm/linux/kernel/git/steve/gfs2-2.6-fixesLinus Torvalds2010-02-122-2/+2
| |\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * git://git.kernel.org/pub/scm/linux/kernel/git/steve/gfs2-2.6-fixes: GFS2: Fix bmap allocation corner-case bug GFS2: Fix error code
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