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The DSA framework has got more picky about always having a phy-mode
for the CPU port. The Armada Ethernet supports RGMII, SGMII,
1000base-x and 2500Base-X. Set the switch phy-mode based on how the
SoC Ethernet ports is been configured. For RGMII mode, have the switch
add the delays.
Additionally, the cpu label has never actually been used in the
binding, so remove it.
Lastly, add a fixed-link node indicating the expected speed/duplex of
the link to the SoC.
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
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The node names should be generic and DT schema expects certain pattern
(e.g. with key/button/switch).
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20220616005333.18491-13-krzysztof.kozlowski@linaro.org
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The node names should be generic and SPI NOR dtschema expects "flash".
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20220407143234.295426-1-krzysztof.kozlowski@linaro.org
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Add the device tree for a Netgear GS110EMX switch featuring 8 Gigabit
ports and 2 Multi-Gig ports (100M/1G/2.5G/5G/10G). An 88E6390X switch
sits at its core connecting to two 88X3310P 10G PHYs. The control plane
is handled by an 88F6811 Armada 381 SoC.
The following functionality is tested:
- 8 gigabit Ethernet ports connecting via 88E6390X to the 88F6811
- serial console UART
- 128 MB commercial grade DDR3L SDRAM
- 16 MB serial SPI NOR flash
The two 88X3310P 10G PHYs while detected during boot seem neither to
detect any link nor pass any traffic.
Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
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