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path: root/arch/arm/boot/dts/bcm958525er.dts
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*-. Merge branches 'next/arm64', 'next/defconfig', 'next/drivers', 'next/dt', ↵Arnd Bergmann2017-03-311-1/+9
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'next/dt64', 'next/fixes-non-critical' and 'next/soc' into for-next * next/arm64: arm64: set CONFIG_MMC_BCM2835=y in defconfig * next/defconfig: multi_v7_defconfig: make Rockchip DRM drivers built-in arm: set CONFIG_MMC_BCM2835=y in bcm2835_defconfig and multi_v7_defconfig ARM: bcm2835: Enable missing CMA settings for VC4 driver * next/drivers: soc: bcm: brcmstb: Match additional compatible strings * next/dt: (98 commits) ARM: dts: augment Moxa ART GPIO node ARM: dts: am335x-baltos: add LED support ARM: dts: omap4-droid4: Fix MMC1 card for detect GPIO and regulator ARM: dts: add PCI to the Gemini device trees ARM: dts: OMAP4460: Thermal: Add slope and offset values ARM: dts: OMAP443x: Thermal: Add slope and offset values ARM: dts: OMAP5: Thermal: Add slope and offset values ARM: dts: DRA7: Thermal: Add slope and offset values ARM: dts: omap3: Add cpu_thermal zone ARM: dts: am437x-gp-evm: Add pinmux for uart0 ARM: dts: am335x-icev2: Add SPI based NOR Documentation: devicetree: mtd: add w25q64 to list of supported SPI flashes ARM: dts: dra7: Add updated operating-points-v2 table for cpu ARM: dts: am4372: Update operating-points-v2 table for cpu ARM: dts: am335x-boneblack: Enable 1GHz OPP for cpu ARM: dts: am33xx: Add updated operating-points-v2 table for cpu ARM: dts: dm8168-evm: add SATA node ARM: dts: dm8168-evm: add the external reference clock for SATA ARM: dts: mvebu: linksys: enable buffer manager support ARM: dts: N9/N950: add bluetooth ... * next/dt64: (29 commits) arm64: dts: move from ARCH_VULCAN to ARCH_THUNDER2 dt-bindings: Add arm64 ARCH_THUNDER2 platform documentation arm64: marvell: dts: add PPv2.2 description to Armada 7K/8K ARM64: dts: marvell: armada-3720 add RTC support ARM64: dts: marvell: armada-3720-db: Add phy for USB3 ARM64: dts: marvell: armada-37xx: Add clock resource for USB3 ARM64: dts: marvell: armada-37xx: Fix interrupt mapping for USB3 arm64: dts: rockchip: add regulator info for Kevin digitizer arm64: dts: rockchip: fix PCIe domain number for rk3399 arm64: dts: rockchip: add rk3399 dw-mmc resets arm64: dts: rockchip: add rk3368 dw-mmc resets arm64: dts: rockchip: disable mailbox of RK3368 SoCs per default arm64: dts: rockchip: add i2s nodes support for RK3368 SoCs arm64: dts: rockchip: add dmac nodes for rk3368 SoCs arm64: dts: rockchip: remove wrongly added idle states on rk3368 arm64: dts: rockchip: describe Gru/Kevin OPPs + CPU regulators arm64: dts: rockchip: add Gru/Kevin DTS dt-bindings: Document rk3399 Gru/Kevin arm64: dts: rockchip: support dwc3 USB for rk3399 arm64: dts: NS2: convert "ok" to "okay" ... * next/fixes-non-critical: MAINTAINERS: Add Stefan Wahren to bcm2835. MAINTAINERS: remove swarren from bcm2835 MAINTAINERS: Add Jon Mason to BCM5301X maintainers * next/soc: ARM: brcmstb: Add entry for 7260 ARM: brcmstb: Enable ARCH_HAS_HOLES_MEMORYMODEL ARM: brcmstb: Enable ZONE_DMA for non 64-bit capable peripherals
| | * ARM: dts: NSP: Add EHCI/OHCI USB nodes to device treeJon Mason2017-03-181-1/+9
| |/ | | | | | | | | | | | | | | Add the EHCI and OHCI entries to the Northstar Plus device tree files. Signed-off-by: Yendapally Reddy Dhananjaya Reddy <yendapally.reddy@broadcom.com> Signed-off-by: Jon Mason <jon.mason@broadcom.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
* | ARM: dts: NSP: GPIO reboot open-sourceJon Mason2017-03-161-0/+1
|/ | | | | | | | | | | | | | | | | The libgpio code pre-sets the GPIO values for the gpio-reset in the device tree. This results in the device being reset during bringup. To prevent this pre-setting, use the "open-source" flag in the device tree. Signed-off-by: Jon Mason <jon.mason@broadcom.com> Fixes: b1aaf88 ("ARM: dts: NSP: Add GPIO reboot method to bcm958625hr DTS file") Fixes: 10baed1 ("ARM: dts: NSP: Add GPIO reboot method to bcm958625xmc DTS file") Fixes: 088e3148 ("ARM: dts: NSP: Add new DT file for bcm958522er") Fixes: e3227c1 ("ARM: dts: NSP: Add new DT file for bcm958525er") Fixes: 2f8bc00 ("ARM: dts: NSP: Add new DT file for bcm958622hr") Fixes: d454c37 ("ARM: dts: NSP: Add new DT file for bcm958623hr") Fixes: f27eacf ("ARM: dts: NSP: Add new DT file for bcm988312hr") Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
* ARM: dts: NSP: Add QSPI support to missing boardsJon Mason2017-01-181-0/+34
| | | | | | | | | | QSPI device tree entries are present in bcm958625k, but missing from bcm958522er, bcm958525er, bcm958525xmc, bcm958622hr, bcm958623hr, bcm958625hr, and bcm988312hr. Duplicate the entry in bcm958625k for all of those that are missing it (as they are identical). Signed-off-by: Jon Mason <jon.mason@broadcom.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
* ARM: dts: NSP: DT Clean-upsJon Mason2017-01-181-1/+0
| | | | | | | | | | | The QSPI entry was added out of the sequental order that the rest of the DTSI file is in. Move it to make it fit in properly. Also, some other entries have been added in a non-alphabetical order in the DTS files, making them different from the other NSP DTS files. Move the relevant peices to make it match. Finally, remove errant new lines. Signed-off-by: Jon Mason <jon.mason@broadcom.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
* ARM: dts: NSP: Add new DT file for bcm958525erJon Mason2016-08-081-0/+142
Create a new device tree file for the Broadcom Northstar Plus bcm958525er SVK. This SVK has 2GB RAM, 2 ports Ethernet, 2 eSATA, 2 PCI slots, and 1 UART. Also, it has the ability to reboot via GPIO. To be added in the future is support for the USB. Signed-off-by: Jon Mason <jon.mason@broadcom.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>