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* ARM: dts: meson8b: odroid-c1: prepare support for the RTCMartin Blumenstingl2019-04-161-0/+14
| | | | | | | | | | | The Odroid-C1 has the 32.768 kHz oscillator (X3 in the schematics) which is required for the RTC. A battery can be connected separately (to the BT1 header) - then the "rtc" node can be enabled manually. By default the RTC is disabled because the boards typically come without the RTC battery. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
* ARM: dts: meson8b: odroidc1: add the GPIO line namesMartin Blumenstingl2019-03-291-0/+52
| | | | | | | | | | | This adds the GPIO line names from the schematics to get them displayed in the debugfs output of each GPIO controller. The schematics from Odroid-C1+ PCB revision 0.4 20150615 are used as referenced. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
* Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/socLinus Torvalds2019-03-061-0/+6
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull ARM SoC device tree updates from Arnd Bergmann: "This is a smaller update than the past few times, but with just over 500 non-merge changesets still dwarfes the rest of the SoC tree. Three new SoC platforms get added, each one a follow-up to an existing product, and added here in combination with a reference platform: - Renesas RZ/A2M (R7S9210) 32-bit Cortex-A9 Real-time imaging processor: https://www.renesas.com/eu/en/products/microcontrollers-microprocessors/rz/rza/rza2m.html - Renesas RZ/G2E (r8a774c0) 64-bit Cortex-A53 SoC "for Rich Graphics Applications": https://www.renesas.com/eu/en/products/microcontrollers-microprocessors/rz/rzg/rzg2e.html - NXP i.MX8QuadXPlus 64-bit Cortex-A35 SoC: https://www.nxp.com/products/processors-and-microcontrollers/arm-based-processors-and-mcus/i.mx-applications-processors/i.mx-8-processors/i.mx-8x-family-arm-cortex-a35-3d-graphics-4k-video-dsp-error-correcting-code-on-ddr:i.MX8X These are actual commercial products we now support with an in-kernel device tree source file: - Bosch Guardian is a product made by Bosch Power Tools GmbH, based on the Texas Instruments AM335x chip - Winterland IceBoard is a Texas Instruments AM3874 based machine used in telescopes at the south pole and elsewhere, see commit d031773169df2 for some pointers: - Inspur on5263m5 is an x86 server platform with an Aspeed ast2500 baseboard management controller. This is for running on the BMC. - Zodiac Digital Tapping Unit, apparently a kind of ethernet switch used in airplanes. - Phicomm K3 is a WiFi router based on Broadcom bcm47094 - Methode Electronics uDPU FTTdp distribution point unit - X96 Max, a generic TV box based on Amlogic G12a (S905X2) - NVIDIA Shield TV (Darcy) based on Tegra210 And then there are several new SBC, evaluation, development or modular systems that we add: - Three new Rockchips rk3399 based boards: - FriendlyElec NanoPC-T4 and NanoPi M4 - Radxa ROCK Pi 4 - Five new i.MX6 family SoM modules and boards for industrial products: - Logic PD i.MX6QD SoM and evaluation baseboad - Y Soft IOTA Draco/Hydra/Ursa family boards based on i.MX6DL - Phytec phyCORE i.MX6 UltraLite SoM and evaluation module - MYIR Tech MYD-LPC4357 development based on the NXP lpc4357 microcontroller - Chameleon96, an Intel/Altera Cyclone5 based FPGA development system in 96boards form factor - Arm Fixed Virtual Platforms(FVP) Base RevC, a purely virtual platform for corresponding to the latest "fast model" - Another Raspberry Pi variant: Model 3 A+, supported both in 32-bit and 64-bit mode. - Oxalis Evalkit V100 based on NXP Layerscape LS1012a, in 96Boards enterprise form factor - Elgin RV1108 R1 development board based on 32-bit Rockchips RV1108 For already supported boards and SoCs, we often add support for new devices after merging the drivers. This time, the largest changes include updates for - STMicroelectronics stm32mp1, which was now formally launched last week - Qualcomm Snapdragon 845, a high-end phone and low-end laptop chip - Action Semi S700 - TI AM654x, their recently merged 64-bit SoC from the OMAP family - Various Amlogic Meson SoCs - Mediatek MT2712 - NVIDIA Tegra186 and Tegra210 - The ancient NXP lpc32xx family - Samsung s5pv210, used in some older mobile phones Many other chips see smaller updates and bugfixes beyond that" * tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (506 commits) ARM: dts: exynos: Fix max voltage for buck8 regulator on Odroid XU3/XU4 dt-bindings: net: ti: deprecate cpsw-phy-sel bindings ARM: dts: am335x: switch to use phy-gmii-sel ARM: dts: am4372: switch to use phy-gmii-sel ARM: dts: dm814x: switch to use phy-gmii-sel ARM: dts: dra7: switch to use phy-gmii-sel arch: arm: dts: kirkwood-rd88f6281: Remove disabled marvell,dsa reference ARM: dts: exynos: Add support for secondary DAI to Odroid XU4 ARM: dts: exynos: Add support for secondary DAI to Odroid XU3 ARM: dts: exynos: Disable ARM PMU on Odroid XU3-lite ARM: dts: exynos: Add stdout path property to Arndale board ARM: dts: exynos: Add minimal clkout parameters to Exynos3250 PMU ARM: dts: exynos: Enable ADC on Odroid HC1 arm64: dts: sprd: Remove wildcard compatible string arm64: dts: sprd: Add SC27XX fuel gauge device arm64: dts: sprd: Add SC2731 charger device arm64: dts: sprd: Add ADC calibration support arm64: dts: sprd: Remove PMIC INTC irq trigger type arm64: dts: rockchip: Enable tsadc device on rock960 ARM: dts: rockchip: add chosen node on veyron devices ...
| * Merge tag 'amlogic-dt' of ↵Arnd Bergmann2019-02-151-0/+5
| |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into arm/dt ARM: dts: Amlogic updates for v5.1 - more features for Endless EC100 board - chip temperature sensor support - fix ethernet pins - add Mali-450 GPU * tag 'amlogic-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic: ARM: dts: meson8b: ec100: add the GPIO line names ARM: dts: meson8b: ec100: improve the description of the regulators ARM: dts: meson8b: ec100: enable the Ethernet PHY interrupt ARM: dts: meson8m2: mxiii-plus: add iio-hwmon for the chip temperature ARM: dts: meson8b: odroidc1: add iio-hwmon for the chip temperature ARM: dts: meson8b: ec100: add iio-hwmon for the chip temperature ARM: dts: meson8b: add the temperature calibration data for the SAR ADC ARM: dts: meson8: add the temperature calibration data for the SAR ADC ARM: dts: meson8m2: use the Meson8m2 specific SAR ADC compatible ARM: dts: meson: switch the clock controller to the HHI register area ARM: dts: meson8b: fix the Ethernet data line signals in eth_rgmii_pins ARM: dts: meson8b: add the Mali-450 MP2 GPU ARM: dts: meson8: add the Mali-450 MP6 GPU dt-bindings: gpu: mali-utgard: add Amlogic Meson8 and Meson8b compatible ARM: dts: meson8b: add the APB bus ARM: dts: meson8: add the APB bus ARM: dts: meson6: add the APB2 bus Signed-off-by: Arnd Bergmann <arnd@arndb.de>
| | * ARM: dts: meson8b: odroidc1: add iio-hwmon for the chip temperatureMartin Blumenstingl2019-02-111-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | SAR ADC enabled channel 8 can be used to measure the chip temperature. This can be made available to the hwmon subsystem by using iio-hwmon. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
| * | ARM: dts: Kill off skeleton{64}.dtsiRob Herring2019-01-301-0/+1
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove the usage of skeleton.dtsi in the remaining dts files. It was deprecated since commit 9c0da3cc61f1 ("ARM: dts: explicitly mark skeleton.dtsi as deprecated"). This will make adding a unit-address to memory nodes easier. The main tricky part to removing skeleton.dtsi is we could end up with no /memory node at all when a bootloader depends on one being present. I hacked up dtc to check for this condition. Acked-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Acked-by: Neil Armstrong <narmstrong@baylibre.com> Acked-by: Antoine Tenart <antoine.tenart@bootlin.com> Acked-by: Alexandre TORGUE <alexandre.torgue@st.com> Acked-by: Robert Jarzmik <robert.jarzmik@free.fr> Acked-by: Vladimir Zapolskiy <vz@mleia.com> Tested-by: Kevin Hilman <khilman@baylibre.com> Reviewed-by: Kevin Hilman <khilman@baylibre.com> Tested-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Rob Herring <robh@kernel.org> Reviewed-by: Gregory CLEMENT <gregory.clement@bootlin.com> Tested-by: Gregory CLEMENT <gregory.clement@bootlin.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* | ARM: dts: meson8b: odroidc1: mark the SD card detection GPIO active-lowMartin Blumenstingl2019-01-101-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | After commit 89a5e15bcba87d ("gpio/mmc/of: Respect polarity in the device tree") SD cards are not detected anymore. The CD GPIO is "active low" on Odroid-C1. The MMC dt-bindings specify: "[...] using the "cd-inverted" property means, that the CD line is active high, i.e. it is high, when a card is inserted". Fix the description of the SD card by marking it as GPIO_ACTIVE_LOW and drop the "cd-inverted" property. This makes the definition consistent with the existing dt-bindings and fixes the check whether an SD card is inserted. Fixes: e03efbce6bebf5 ("ARM: dts: meson8b-odroidc1: add microSD support") Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Tested-by: Anand Moon <linux.amoon@gmail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
* | arm: dts: meson: Fix IRQ trigger type for macirqCarlo Caione2019-01-101-1/+0
|/ | | | | | | | | | | | | | | | | | | | | | | | A long running stress test on a custom board shipping an AXG SoCs and a Realtek RTL8211F PHY revealed that after a few hours the connection speed would drop drastically, from ~1000Mbps to ~3Mbps. At the same time the 'macirq' (eth0) IRQ would stop being triggered at all and as consequence the GMAC IRQs never ACKed. After a painful investigation the problem seemed to be due to a wrong defined IRQ type for the GMAC IRQ that should be LEVEL_HIGH instead of EDGE_RISING. The change in the macirq IRQ type also solved another long standing issue affecting this SoC/PHY where EEE was causing the network connection to die after stressing it with iperf3 (even though much sooner). It's now possible to remove the 'eee-broken-1000t' quirk as well. Fixes: 9c15795a4f96 ("ARM: dts: meson8b-odroidc1: ethernet support") Signed-off-by: Carlo Caione <ccaione@baylibre.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Tested-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
* ARM: dts: meson8b: odroidc1: add stdout-path propertyMartin Blumenstingl2018-09-261-0/+4
| | | | | | | | | | To use the "earlycon" kernel command line parameter (without arguments) we need a stdout-path property under the /chosen node. Add this to make it easier to spot errors early in the boot process when looking for them. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
* ARM: dts: meson8b: odroidc1: enable the SAR ADCMartin Blumenstingl2018-09-261-0/+5
| | | | | | | | | | Odroid-C1 exposes ADC channels 0 and 1 on the GPIO headers. NOTE: Due to the SoC design these are limited to 1.8V (instead of 3.3V like all other pins). Enable the SAR ADC to enable voltage measurements on these pins. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
* ARM: dts: meson8b: odroidc1: add the fixed voltage regulatorsMartin Blumenstingl2018-09-261-0/+73
| | | | | | | | | | | | | | | | | | | | | | | | | | There are multiple fixed regulators on the Odroid-C1 board. Add them so they can be used when we add the devices that need them (SAR ADC needs the 1.8V IOREF, RTC needs VDD_RTC). These are: - P5V0 is the main 5V power input - VCC3V3 / VDDIO_AO3V3 / VDD3V3: fixed regulator with 3.3V output which is supplied by P5V0 - IOREF_1V8 / VCC1V8 / VDD1V8: fixed regulator with 1.8V output which is supplied by P5V0 - VDD_RTC: fixed voltage regulator with 0.9V output which is supplied by VDDIO_AO3V3 - DDR_VDDC / DDR3_1V5: fixed voltage regulator with 1.5V output which is supplied by P5V0 - the existing TF_IO and RFLASH_VDD_EN regulators are supplied by VDDIO_AO3V3 - the existing VCCK regulator is supplied by P5V0 This does not add the missing VDDEE regulator (controlled by PWM_D) because it's not clear yet how to configure the voltage of that regulator. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
* ARM: dts: meson8b: odroidc1: add the CPU voltage regulatorMartin Blumenstingl2018-09-261-0/+27
| | | | | | | | | | | | | | | | | | The CPU voltage regulator is a "Monolithic Power Systems MP2161" (according to the Odroid-C1+'s schematics). It is driven by PWM_C on GPIODV_9. Hardkernel's 3.10 kernel (based on the Amlogic GPL kernel sources) defines a PWM voltage table with the following values: - 0.86 volts = PWM register value 0x10f001b - (more values in 0.1 volt increments) - 1.14 volts = PWM register value 0x000012a When using the XTAL (24MHz) as input this translates into a PWM period of 12218ns with 0.86V using a duty cycle of 91% and 1.14V using a duty cycle of 0%. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
* ARM: dts: meson8b: odroid-c1: enable the IR receiverMartin Blumenstingl2018-05-091-0/+6
| | | | | | | | The Odroid-C1 comes with an IR receiver. It is connected to the GPIOAO_7 pin and thus using the SoC's internal IR decoder. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
* ARM: dts: meson8b: odroid-c1: sort nodes alphabeticallyMartin Blumenstingl2018-05-091-34/+34
| | | | | | | This makes it easier to find existing nodes. No functional changes. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
* ARM: dts: meson8b-odroidc1: add microSD supportLinus Lüssing2018-03-201-0/+58
| | | | | | | | The Odroid C1 features a microSD slot. This patch adds the necessary DT bindings to support it. Signed-off-by: Linus Lüssing <linus.luessing@c0d3.blue> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
* ARM: dts: meson8b-odroidc1: ethernet supportEmiliano Ingrassia2018-02-121-0/+30
| | | | | | | | | | | | | | | The Odroid-C1+ board is equipped with an RTL8211F ethernet PHY which supports 10/100/1000 Mbps ethernet. The PHY reset and interrupt lines are controlled by the SoC via two GPIO lines (GPIOH_4 and GPIOH_3 respectively). The PHY energy efficient ethernet (eee) mode is marked as broken using "eee-broken-1000t" because, during tests, high packet losses were experienced without it. Signed-off-by: Emiliano Ingrassia <ingrassia@epigenesys.com> Tested-by: Linus Lüssing <linus.luessing@c0d3.blue> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
* ARM: dts: meson: enabling the USB Host controller on Odroid-C1/C1+ boardEmiliano Ingrassia2017-10-061-0/+23
| | | | | | | | | | This patch enables the USB Host controller (USB1) and the relative USB2 PHY on Odroid-C1/C1+ board. Signed-off-by: Emiliano Ingrassia <ingrassia@epigenesys.com> Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Tested-by: Linus Lüssing <linus.luessing@c0d3.blue> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
* ARM: meson: Add status LED for Odroid-C1Edward Cragg2016-01-041-0/+11
| | | | | | | Add the blue status LED to the Hardkernel Odroid C1 board DTS. Signed-off-by: <edward.cragg@codethink.co.uk> Signed-off-by: Carlo Caione <carlo@endlessm.com>
* ARM: meson: Add DTS for Odroid-C1 and Tronfy MXQ boardsCarlo Caione2015-10-081-0/+67
Signed-off-by: Carlo Caione <carlo@endlessm.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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