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* ARM: dts: suniv: Add Lctech Pi F1C200s devicetreeAndre Przywara2023-03-231-0/+6
| | | | | | | | | | | | | | | | | | | | The Lctech Pi F1C200s (also previously known under the Cherry Pi brand) is a small development board with the Allwinner F1C200s SoC. This is the same as the F1C100s, but with 64MB instead of 32MB co-packaged DRAM. Alongside the obligatory micro-SD card slot, the board features a SPI-NAND flash chip, LCD and touch connectors, and unpopulated expansion header pins. There are two USB Type-C ports on the board: One supplies the power, also connects to the USB MUSB OTG controller port. The other one is connected to an CH340 USB serial chip, which in turn is connected to UART1. Add a devicetree file, so that the board can be used easily. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://lore.kernel.org/r/20230319212936.26649-7-andre.przywara@arm.com Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
* ARM: dts: suniv: add USB-related device nodesIcenowy Zheng2023-03-231-0/+26
| | | | | | | | | | | | | | The suniv SoC has a USB OTG controller and a USB PHY like other Allwinner SoCs. Add their device tree node. Signed-off-by: Icenowy Zheng <uwu@icenowy.me> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> Link: https://lore.kernel.org/r/20230319212936.26649-2-andre.przywara@arm.com Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
* ARM: dts: suniv: f1c100s: add LRADC nodeAndre Przywara2022-11-161-0/+8
| | | | | | | | | | | | | | | | | The Allwinner F1C100s series of SoCs contain a LRADC (aka. KEYADC) compatible to the version in other SoCs. The manual doesn't mention the ratio of the input voltage that is used, but comparing actual measurements with the values in the register suggests that it is 3/4 of Vref. Add the DT node describing the base address and interrupt. As in the older SoCs, there is no explicit reset or clock gate, also there is a dedicated, non-multiplexed pin, so need for more properties. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://lore.kernel.org/r/20221107005433.11079-8-andre.przywara@arm.com Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
* ARM: dts: suniv: f1c100s: add CIR DT nodeAndre Przywara2022-11-161-0/+11
| | | | | | | | | | | | | | | The CIR (infrared receiver) controller in the Allwinner F1C100s series of SoCs is compatible to the ones used in other Allwinner SoCs. Add the DT node describing the resources of the controller. There are multiple possible pinmuxes, but none as them seem to be an obvious choice, so refrain from adding any pincontroller subnodes for now. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://lore.kernel.org/r/20221107005433.11079-7-andre.przywara@arm.com Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
* ARM: dts: suniv: f1c100s: add I2C DT nodesAndre Przywara2022-11-161-0/+42
| | | | | | | | | | | | | | The Allwinner F1C100s series of SoCs contain three I2C controllers compatible to the ones used in other Allwinner SoCs. Add the DT nodes describing the resources of the controllers. At least one board connects an on-board I2C chip to PD0/PD12 (I2C0), so include those pins already, to simplify referencing them later. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://lore.kernel.org/r/20221107005433.11079-4-andre.przywara@arm.com Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
* ARM: dts: suniv: f1c100s: add PWM nodeAndre Przywara2022-11-161-0/+9
| | | | | | | | | | | | | | The Allwinner F1C100s family of SoCs contain a PWM controller compatible to the one used in the A20 chip. Add the DT node so that any users can simply enable it in their board DT. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Thierry Reding <thierry.reding@gmail.com> Reviewed-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://lore.kernel.org/r/20221107005433.11079-3-andre.przywara@arm.com Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
* ARM: dts: suniv: F1C100: add SPI supportAndre Przywara2022-04-061-0/+33
| | | | | | | | | | | | | | | | | | | | The F1C100 series contains two SPI controllers, and many boards use SPI0 for a SPI flash, as the BROM is able to boot from that. Describe the two controllers in the SoC .dtsi, and also add the PortC pins for SPI0, since this is where BROM looks at when trying to boot from the commonly used SPI flash. The SPI controller seems to be the same as in the H3 chips, but it lacks a separate mod clock. The manual says it's connected to AHB directly. We don't export that AHB clock directly, but can use the AHB *gate* clock as a clock source, since the SPI driver is not supposed to change the AHB frequency anyway. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://lore.kernel.org/r/20220317162349.739636-12-andre.przywara@arm.com
* ARM: dts: suniv: F1C100: add MMC controllersJesse Taube2022-04-061-0/+42
| | | | | | | | | | | | | | | | The F1C100 series contains two MMC controllers, where the first one is typically connected to an (micro)SD card slot (as this is the one the BROM is able to boot from). Describe the two controllers in the SoC .dtsi. We also add the pinctrl description for MMC0, since this is the only pin set supporting that function anyway, and SD cards are very common across boards. Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://lore.kernel.org/r/20220317162349.739636-9-andre.przywara@arm.com
* ARM: dts: suniv: F1C100: fix timer nodeAndre Przywara2022-04-061-1/+1
| | | | | | | | | | | | The Allwinner F1C100s has three timer instances, each with their own interrupt line. Add the missing two interrupts to the DT node, to match the DT binding. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://lore.kernel.org/r/20220317162349.739636-8-andre.przywara@arm.com
* ARM: dts: suniv: F1C100: fix CPU nodeAndre Przywara2022-04-061-1/+5
| | | | | | | | | | | | | The /cpu node in the f1c100s.dtsi is not spec compliant, it's missing the reg property, and the corresponding address and size cells properties. Add them to make the bindings check pass. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://lore.kernel.org/r/20220317162349.739636-7-andre.przywara@arm.com
* ARM: dts: suniv: F1C100: add clock and reset macrosJesse Taube2022-04-061-7/+10
| | | | | | | | | | | Include clock and reset macros and replace magic numbers. Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://lore.kernel.org/r/20220317162349.739636-6-andre.przywara@arm.com
* ARM: dts: suniv: F1C100: fix watchdog compatibleAndre Przywara2022-04-061-1/+3
| | | | | | | | | | | | | | | | | | | | | | The F1C100 series of SoCs actually have their watchdog IP being compatible with the newer Allwinner generation, not the older one. The currently described sun4i-a10-wdt actually does not work, neither the watchdog functionality (just never fires), nor the reset part (reboot hangs). Replace the compatible string with the one used by the newer generation. Verified to work with both the watchdog and reboot functionality on a LicheePi Nano. Also add the missing interrupt line and clock source, to make it binding compliant. Fixes: 4ba16d17efdd ("ARM: dts: suniv: add initial DTSI file for F1C100s") Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://lore.kernel.org/r/20220317162349.739636-4-andre.przywara@arm.com
* ARM: dts: suniv: Fix improper bindings include patchMaxime Ripard2018-12-201-3/+0
| | | | | | | | | | The clock and reset bindings are going through different trees, and while the patch doesn't contain any value defined in that header, it still includes those files and result in a build breakage when building the DT without the matching clock and reset patches applied. Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* ARM: dts: suniv: add initial DTSI file for F1C100sMesih Kilinc2018-12-041-0/+147
F1C100s is one product with the suniv die, which has a 32MiB co-packaged DDR1 DRAM chip. As we have the support for suniv pin controller and CCU now, add a initial DTSI for it. Signed-off-by: Mesih Kilinc <mesihkilinc@gmail.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
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