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* Merge remote-tracking branch 'pinctrl/for-next'Stephen Rothwell2017-04-071-1/+1
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| * Merge branch 'devel' into for-nextLinus Walleij2017-04-071-1/+1
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| | * pinctrl: rockchip: rename RK1108 to RV1108Andy Yan2017-03-231-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Rockchip finally named the SOC as RV1108, so change it. Signed-off-by: Andy Yan <andy.yan@rock-chips.com> [adapted rk1108 dtsi to keep bisectability] Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | | Merge remote-tracking branch 'crypto/master'Stephen Rothwell2017-04-072-0/+11
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| * | | ARM: dts: stm32: enable CRC on stm32746g-eval boardFabien DESSENNE2017-04-051-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable the CRC (CRC32 crypto) on stm32746g-eval board Signed-off-by: Fabien Dessenne <fabien.dessenne@st.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
| * | | ARM: dts: stm32: Add CRC support to stm32f746Fabien DESSENNE2017-04-051-0/+7
| | |/ | |/| | | | | | | | | | | | | | | | Add CRC (CRC32 crypto) support to stm32f746. Signed-off-by: Fabien Dessenne <fabien.dessenne@st.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* | | Merge remote-tracking branch 'pm/linux-next'Stephen Rothwell2017-04-071-5/+0
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| *-. \ \ Merge branches 'pm-cpufreq', 'pm-cpufreq-sched' and 'intel_pstate' into ↵Rafael J. Wysocki2017-04-061-5/+0
| |\ \ \ \ | | | |/ / | | |_| / | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | linux-next * pm-cpufreq: cpufreq: dbx500: Manage cooling device from cpufreq driver MAINTAINERS: Add file patterns for cpufreq device tree bindings cpufreq: qoriq: enhance bus frequency calculation cpufreq: mediatek: Add support for MT8176 and MT817x cpufreq: mt8173: Mark mt8173_cpufreq_driver_init as __init * pm-cpufreq-sched: cpufreq: schedutil: Trace frequency only if it has changed cpufreq: schedutil: Avoid reducing frequency of busy CPUs prematurely cpufreq: schedutil: Refactor sugov_next_freq_shared() cpufreq: schedutil: Redefine the rate_limit_us tunable * intel_pstate: (22 commits) cpufreq: intel_pstate: Add support for Gemini Lake cpufreq: intel_pstate: Eliminate intel_pstate_get_min_max() cpufreq: intel_pstate: Do not walk policy->cpus cpufreq: intel_pstate: Introduce pid_in_use() cpufreq: intel_pstate: Drop struct cpu_defaults cpufreq: intel_pstate: Move cpu_defaults definitions cpufreq: intel_pstate: Add update_util callback to pstate_funcs cpufreq: intel_pstate: Use different utilization update callbacks cpufreq: intel_pstate: Modify check in intel_pstate_update_status() cpufreq: intel_pstate: Drop driver_registered variable cpufreq: intel_pstate: Skip unnecessary PID resets on init cpufreq: intel_pstate: Set HWP sampling interval once cpufreq: intel_pstate: Clean up intel_pstate_busy_pid_reset() cpufreq: intel_pstate: Fold intel_pstate_reset_all_pid() into the caller cpufreq: intel_pstate: Initialize pid_params statically cpufreq: intel_pstate: Drop pointless initialization of PID parameters cpufreq: intel_pstate: Eliminate struct perf_limits cpufreq: intel_pstate: Avoid transient updates of cpuinfo.max_freq cpufreq: intel_pstate: Active mode P-state limits rework cpufreq: intel_pstate: Use load-based P-state selection more widely ...
| | * | cpufreq: dbx500: Manage cooling device from cpufreq driverViresh Kumar2017-03-161-5/+0
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The best place to register the CPU cooling device is from the cpufreq driver as we would know if all the resources are already available or not. That's what is done for the cpufreq-dt.c driver as well. The cpu-cooling driver for dbx500 platform was just (un)registering with the thermal framework and that can be handled easily by the cpufreq driver as well and in proper sequence as well. Get rid of the cooling driver and its its users and manage everything from the cpufreq driver instead. Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Tested-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
* | | Merge remote-tracking branch 'sunxi/sunxi/for-next'Stephen Rothwell2017-04-0788-1537/+1482
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| *---. \ \ Merge branches 'sunxi/clk-for-4.12', 'sunxi/dt-for-4.12' and ↵Maxime Ripard2017-04-065-31/+128
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| | | * | | ARM: sun8i: sina33: add highest OPP of CPUsQuentin Schulz2017-04-051-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The A33 supports 1.1GHz and 1.2GHz frequencies at 1.32V and the Sinlinx SinA33 has its cpu-supply property set in the cpu DT node. Therefore, CPUfreq knows how to handle the regulator in charge of the CPU and can adjust its voltage to match the OPP. Add these two CPU frequencies to the CPU OPP table of the Sinlinx SinA33. Signed-off-by: Quentin Schulz <quentin.schulz@free-electrons.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| | | * | | ARM: sun8i: a33: Add devfreq-based GPU coolingMaxime Ripard2017-04-052-0/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds GPU thermal throttling for the Allwinner A33. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Quentin Schulz <quentin.schulz@free-electrons.com>
| | | * | | ARM: sun8i: a33: add CPU thermal throttlingQuentin Schulz2017-04-051-0/+45
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds CPU thermal throttling for the Allwinner A33. It uses the thermal sensor present in the SoC's GPADC. Signed-off-by: Quentin Schulz <quentin.schulz@free-electrons.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| | | * | | ARM: sun8i: a33: add thermal sensorQuentin Schulz2017-04-051-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds the DT node for the thermal sensor present in the Allwinner A33 GPADC. Signed-off-by: Quentin Schulz <quentin.schulz@free-electrons.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| | | * | | ARM: dts: sun7i: fix device node orderingPatrick Menschel2017-04-051-15/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch changes the device node position of ps20 and ps21 to fix ordering by rising physical address. From uart7: serial@01c29c00 i2c0: i2c@01c2ac00 i2c1: i2c@01c2b000 i2c2: i2c@01c2b400 i2c3: i2c@01c2b800 i2c4: i2c@01c2c000 gmac: ethernet@01c50000 hstimer@01c60000 gic: interrupt-controller@01c81000 ps20: ps2@01c2a000 ps21: ps2@01c2a400 to uart7: serial@01c29c00 ps20: ps2@01c2a000 ps21: ps2@01c2a400 i2c0: i2c@01c2ac00 i2c1: i2c@01c2b000 i2c2: i2c@01c2b400 i2c3: i2c@01c2b800 i2c4: i2c@01c2c000 gmac: ethernet@01c50000 hstimer@01c60000 gic: interrupt-controller@01c81000 Signed-off-by: Patrick Menschel <menschel.p@posteo.de> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| | | * | | ARM: dts: sun4i: fix device node orderingPatrick Menschel2017-04-051-16/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch changes the device node position of ps20 and ps21 to fix ordering by rising physical address. From uart7: serial@01c29c00 i2c0: i2c@01c2ac00 i2c1: i2c@01c2b000 i2c2: i2c@01c2b400 ps20: ps2@01c2a000 ps21: ps2@01c2a400 to uart7: serial@01c29c00 ps20: ps2@01c2a000 ps21: ps2@01c2a400 i2c0: i2c@01c2ac00 i2c1: i2c@01c2b000 i2c2: i2c@01c2b400 Signed-off-by: Patrick Menschel <menschel.p@posteo.de> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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| *---. \ \ \ \ Merge branches 'sunxi/clk-for-4.12', 'sunxi/dt-for-4.12', ↵Maxime Ripard2017-04-043-31/+41
| |\ \ \ \ \ \ \ | | | |_|/ / / / | | |/| | / / / | | | | |/ / / | | | |/| | | 'sunxi/dt-split-h5-for-4.12' and 'sunxi/dt64-for-4.12' into sunxi/for-next
| | | | * | | ARM: sunxi: h3/h5: switch apb0-related clocks to r_ccuIcenowy Zheng2017-04-041-31/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now we have driver for the PRCM CCU, switch to use it instead of old-style clock nodes for apb0-related clocks in sunxi-h3-h5.dtsi . The mux 3 of R_CCU is still the internal oscillator, which is said to be 16MHz plus minus 30%, and get a measured value of 15MHz~16MHz on my two H3 boards and one H5 board. Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| | | * | | | ARM: dts: sun7i: Add can0_pins_a pinctrl settingsPatrick Menschel2017-04-041-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The A20 SoC has an on-board CAN controller. This patch adds the pinctrl settings for pins PH20 and PH21. This patch is adapted from the description in Documentation/devicetree/bindings/net/can/sun4i_can.txt Signed-off-by: Patrick Menschel <menschel.p@posteo.de> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| | | * | | | ARM: dts: sun7i: Add CAN nodePatrick Menschel2017-04-041-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The A20 SoC has an on-board CAN controller. This patch adds the device node. The CAN controller is inherited from the A10 SoC and uses the same driver. This patch is adapted from the description in Documentation/devicetree/bindings/net/can/sun4i_can.txt Signed-off-by: Patrick Menschel <menschel.p@posteo.de> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| | | * | | | ARM: dts: sun4i: Add can0_pins_a pinctrl settingsPatrick Menschel2017-04-041-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The A10 SoC has an on-board CAN controller. This patch adds the pinctrl settings for pins PH20 and PH21. This patch is adapted from the description in Documentation/devicetree/bindings/net/can/sun4i_can.txt Signed-off-by: Patrick Menschel <menschel.p@posteo.de> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| | | * | | | ARM: dts: sun4i: Add CAN nodePatrick Menschel2017-04-041-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The A10 SoC has an on-board CAN controller. This patch adds the device node. This patch is adapted from the description in Documentation/devicetree/bindings/net/can/sun4i_can.txt Signed-off-by: Patrick Menschel <menschel.p@posteo.de> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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| *-----. \ \ \ \ \ Merge branches 'sunxi/clk-fixes-for-4.11', 'sunxi/clk-for-4.12', ↵Maxime Ripard2017-04-0389-1518/+1349
| |\ \ \ \ \ \ \ \ \ | | |_|_|_|/ / / / / | |/| | | | / / / / | | | |_|_|/ / / / | | |/| | | / / / | | | | | |/ / / | | | | |_| / / | | | |/| | / 'sunxi/config64-for-4.12', 'sunxi/core-for-4.12', 'sunxi/defconfig-for-4.12', 'sunxi/dt-for-4.12', 'sunxi/fixes-for-4.11', 'sunxi/dt-split-h3-for-4.12' and 'sunxi/dt-split-h5-for-4.12' into sunxi/for-next
| | | | * | | ARM: sun8i: h2+: enable USB OTG for Orange Pi Zero boardIcenowy Zheng2017-03-271-1/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Orange Pi Zero board features a USB OTG port, which has a ID pin, and can be used to power up the board. However, even if the board is powered via +5V pin in GPIO/expansion headers, the VBUS in the OTG port cannot be powered up, thus it's impossible to use it in host mode with simple OTG cables. Add support for it in peripheral mode. If someone really want to use it in host mode, the mode of PHY can be switch via sysfs, then use a powered USB OTG cable or powered USB HUB to power up external USB devices. Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| | | | * | | ARM: sun8i: h3: enable USB OTG on Orange Pi OneIcenowy Zheng2017-03-271-1/+21
| | | | |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Orange Pi One features a MicroUSB port that can work in both host mode and peripheral mode. When in host mode, its VBUS is controlled via a GPIO; when in peripheral mode, its VBUS cannot be used to power up the board. Add support for this port. Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| | | | * | ARM: sunxi: h3/h5: add usb_otg and OHCI/EHCI for usbc0 on H3/H5Icenowy Zheng2017-03-271-0/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Allwinner H3/H5 have a dual-routed USB PHY0 -- routed to either OHCI/EHCI or MUSB controller. Add device nodes for these controllers. Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| | | | * | arm: sun8i: h3: split Allwinner H3 .dtsiAndre Przywara2017-03-272-559/+626
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The new Allwinner H5 SoC is pin-compatible to the H3 SoC, but with the Cortex-A7 cores replaced by Cortex-A53 cores and the MMC controller updated. So we should really share almost the whole .dtsi. In preparation for that move the peripheral parts of the existing sun8i-h3.dtsi into a new sunxi-h3-h5.dtsi. The actual sun8i-h3.dtsi then includes that and defines the H3 specific parts on top of it. Signed-off-by: Andre Przywara <andre.przywara@arm.com> [Icenowy: also split out mmc and gic, as well as pio and ccu's compatible, and make drop of skeleton into a seperated patch] Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| | | | * | arm: sun8i: h3: correct the GIC compatible in H3 to gic-400Icenowy Zheng2017-03-271-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to the datasheets provided by Allwinner, both Allwinner H3 and H5 use GIC-400 as their interrupt controller. For better device tree reusing, correct the GIC compatible in H3 DTSI to "arm,gic-400", thus this node can be reused in H5. Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| | | | * | arm: sun8i: h3: drop pinctrl-a10.h inclusion for H3 DTSIIcenowy Zheng2017-03-271-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | After converting to generic pinconf binding, pinctrl-a10.h is now not used at all. Drop its inclusion for H3 DTSI. Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| | | | * | arm: sun8i: h3: drop skeleton.dtsi inclusion in H3 DTSIIcenowy Zheng2017-03-271-2/+0
| | |_|/ / | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The skeleton.dtsi file is now deprecated, and do not exist in ARM64 environment. Since we will soon reuse most part of H3 DTSI for H5, which is an ARM64 chip, drop skeleton.dtsi inclusion now. Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| | | * | ARM: sun8i: a33: add operating-points-v2 property to all nodesQuentin Schulz2017-03-221-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The OPP are declared as shared but no operating points are declared for cpu1, 2 and 3. Thus, the following error happens during the boot: cpu cpu1: dev_pm_opp_of_get_sharing_cpus: Couldn't find tcpu_dev node. This patch applies the operating points to each cpu of the A33. Fixes: 03749eb88e63 ("ARM: dts: sun8i: add opp-v2 table for A33") Signed-off-by: Quentin Schulz <quentin.schulz@free-electrons.com> Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| | | * | ARM: sun8i: a33: remove highest OPP to fix CPU crashesQuentin Schulz2017-03-211-6/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The highest supported frequency (1.2GHz) requires to "overvolt" the CPU. However, some boards still do not have the cpu-supply DT property in the cpu DT node which means that the CPU will always run with the same input voltage but try to run at 1.2GHz frequency. This is the source of (experienced) CPU crashes. Remove the OPP which requires overvolting the CPU until all boards have a cpu-supply property. Fixes: 03749eb88e63 ("ARM: dts: sun8i: add opp-v2 table for A33") Signed-off-by: Quentin Schulz <quentin.schulz@free-electrons.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| | * | | ARM: sun7i: cubietruck: enable ACIN und USB power supply subnodeAlexander Syring2017-04-031-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Cubietruck has an AXP209 PMIC and can be power-supplied by ACIN via the CHG-IN pin or by USB. This enables the ACIN and the USB power supply subnode in the DT. Signed-off-by: Alexander Syring <alex@asyring.de> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| | * | | ARM: dts: sun5i: Add interrupt for display backendChen-Yu Tsai2017-03-291-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The display backend on sun5i shares the same interrupt line as the display frontend. Add it. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| | * | | ARM: dts: sun7i: Use axp209.dtsi on A20-OLinuXino-MicroEzequiel Garcia2017-03-271-4/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit makes use of the axp209.dtsi file to define the AXP209 PMIC. While here, define the rails that are enabled on this board. Tested checking the regulator voltage varies according to the CPU frequency. Signed-off-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| | * | | ARM: dts: sun6i: sina31s: Enable SPDIF outChen-Yu Tsai2017-03-271-0/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The SinA31s has a coaxial SPDIF output. Enable it. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| | * | | ARM: sun8i: sina33: add cpu-supplyQuentin Schulz2017-03-271-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds the cpu-supply DT property to the cpu0 DT node needed by the board to adapt the regulator voltage depending on the currently used OPP. Signed-off-by: Quentin Schulz <quentin.schulz@free-electrons.com> Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| | * | | ARM: sun8i: a33: add all operating pointsQuentin Schulz2017-03-271-0/+54
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds almost all operating points allowed for the A33 as defined by fex files available at: https://github.com/linux-sunxi/sunxi-boards/tree/master/sys_config/a33 There are more possible frequencies in this patch than there are in the fex files because the fex files only give an interval of possible frequencies for a given voltage. All supported frequencies are defined in the original driver code in Allwinner vendor tree. There are two missing frequencies though: 1104MHz and 1200MHz which require the CPU to have 1.32V supplied, which is higher than the default voltage. Without all A33 boards defining the CPU regulator, we cannot have these two frequencies as it would cause the CPU to try to run a higher frequency without "overvolting" which is very likely to crash the CPU. Therefore, these two frequencies must be enabled on a per-board basis. Signed-off-by: Quentin Schulz <quentin.schulz@free-electrons.com> Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| | * | | ARM: sun5i: chip: enable ACIN power supply subnodeQuentin Schulz2017-03-271-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The NextThing Co. CHIP has an AXP209 PMIC and can be power-supplied by ACIN via the CHG-IN pin. This enables the ACIN power supply subnode in the DT. Signed-off-by: Quentin Schulz <quentin.schulz@free-electrons.com> Acked-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| | * | | ARM: dts: sun8i: sina33: enable ACIN power supply subnodeQuentin Schulz2017-03-271-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Sinlinx SinA33 has an AXP223 PMIC and an ACIN connector, thus, we enable the ACIN power supply in its Device Tree. Signed-off-by: Quentin Schulz <quentin.schulz@free-electrons.com> Acked-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| | * | | ARM: dtsi: axp22x: add AC power supply subnodeQuentin Schulz2017-03-271-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The X-Powers AXP22X PMIC exposes the status of AC power supply. This adds the AC power supply subnode for the AXP22X PMIC. Signed-off-by: Quentin Schulz <quentin.schulz@free-electrons.com> Acked-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| | * | | ARM: dtsi: axp209: add AC power supply subnodeQuentin Schulz2017-03-271-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The X-Powers AXP20X PMIC exposes the status of AC power supply, the current current and voltage supplied to the board by the AC power supply. This adds the AC power supply subnode for AXP20X PMIC. Signed-off-by: Quentin Schulz <quentin.schulz@free-electrons.com> Acked-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| | * | | ARM: dts: sunxi: Remove no longer used pinctrl/sun4i-a10.h headerChen-Yu Tsai2017-03-2775-78/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | All dts files for the sunxi platform have been switched to the generic pinconf bindings. As a result, the sunxi specific pinctrl macros are no longer used. Remove the #include entry with the following command: sed --follow-symlinks -i -e '/pinctrl\/sun4i-a10.h/D' \ arch/arm/boot/dts/sun?i*.* arch/arm/boot/dts/sun9i-a80.dtsi was then edited to remove the extra empty line. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| | * | | ARM: dts: sun8i-a23-q8-tablet: Drop pinmux setting for codec PA gpioChen-Yu Tsai2017-03-271-10/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The old sunxi specific pinctrl bindings are deprecated, in favor of the new generic pinconf bindings. Also, we are moving towards handling GPIO pinmux settings that don't require extra bias or drive strength settings to use the GPIO bindings only. This patch removes the last instance of the sunxi specific pinctrl bindings that use the pinctrl header by dropping the pinmux setting for the audio codec's PA (external amplifier) control GPIO. The pin is pulled down externally. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| | * | | ARM: sun8i: a33: Add the Mali OPPsMaxime Ripard2017-03-061-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Mali GPU in the A33 has various operating frequencies used in the Allwinner BSP. Add them to our DT. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| | * | | ARM: dts: sunxi: Add regulators for Sinovoip BPI-M2Emmanuel Vadot2017-03-061-0/+57
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the needed node for DFVS on Sinovoip BPI-M2. This add the axp221 under the p2wi node, the regulators and the cpu-supply property for cpu0. Signed-off-by: Emmanuel Vadot <manu@bidouilliste.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| | * | | ARM: dts: sun8i-h3: Add mmc2 node to the X2Marcus Cooper2017-03-061-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Beelink X2 has an on-board eMMC so add a node enabling the mmc2 controller. Signed-off-by: Marcus Cooper <codekipper@gmail.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| | * | | ARM: sun7i: Enable audio codec on A20-OLinuXino-MicroJonathan Liu2017-03-061-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The A20-OLinuXino-Micro has 3.5 mm sockets for headphone output and microphone input. Signed-off-by: Jonathan Liu <net147@gmail.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| | * | | ARM: dts: sun8i: Add dts file for NanoPi NEO AirJelle van der Waa2017-03-062-0/+98
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | add support for the NanoPi NEO Air H3 board from friendlyarm.com . This board contains WiFi, Bluetooth, 8GB eMMC storage and 512 MB DDR3 ram. Signed-off-by: Jelle van der Waa <jelle@vdwaa.nl> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>