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path: root/arch/x86/events/perf_event.h
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* perf/x86/intel: Apply mid ACK for small coreKan Liang2021-08-061-0/+15
* perf/x86/amd: Don't touch the AMD64_EVENTSEL_HOSTONLY bit inside the guestLike Xu2021-08-041-1/+2
* Merge tag 'perf-core-2021-06-28' of git://git.kernel.org/pub/scm/linux/kernel...Linus Torvalds2021-06-281-0/+1
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| * perf/x86: Reset the dirty counter to prevent the leak for an RDPMC taskKan Liang2021-06-171-0/+1
* | perf/x86/lbr: Remove cpuc->lbr_xsave allocation from atomic contextLike Xu2021-05-181-0/+6
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* perf/x86/intel: Add Alder Lake Hybrid supportKan Liang2021-04-191-0/+7
* perf/x86: Support filter_match callbackKan Liang2021-04-191-0/+1
* perf/x86: Add structures for the attributes of Hybrid PMUsKan Liang2021-04-191-0/+19
* perf/x86: Register hybrid PMUsKan Liang2021-04-191-0/+14
* perf/x86: Factor out x86_pmu_show_pmu_capKan Liang2021-04-191-0/+3
* perf/x86: Hybrid PMU support for extra_regsKan Liang2021-04-191-0/+1
* perf/x86: Hybrid PMU support for event constraintsKan Liang2021-04-191-0/+2
* perf/x86: Hybrid PMU support for hardware cache eventKan Liang2021-04-191-0/+9
* perf/x86: Hybrid PMU support for unconstrainedKan Liang2021-04-191-0/+11
* perf/x86: Hybrid PMU support for countersKan Liang2021-04-191-0/+4
* perf/x86: Hybrid PMU support for intel_ctrlKan Liang2021-04-191-2/+8
* perf/x86/intel: Hybrid PMU support for perf capabilitiesKan Liang2021-04-191-0/+33
* perf/x86: Track pmu in per-CPU cpu_hw_eventsKan Liang2021-04-191-1/+3
* perf/x86: Move cpuc->running into P4 specific codeKan Liang2021-04-161-1/+0
* perf/x86/intel: Support CPUID 10.ECX to disable fixed countersKan Liang2021-02-011-0/+5
* perf/x86/intel: Add perf core PMU support for Sapphire RapidsKan Liang2021-02-011-1/+11
* perf/x86/intel: Filter unsupported Topdown metrics eventKan Liang2021-02-011-0/+1
* perf/intel: Remove Perfmon-v4 counter_freezing supportPeter Zijlstra2021-01-271-2/+1
* Merge remote-tracking branch 'origin/master' into perf/corePeter Zijlstra2020-11-261-1/+2
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| * perf/x86/intel: Make anythread filter support conditionalStephane Eranian2020-11-091-0/+1
| * perf/x86: Reduce stack usage for x86_pmu::drain_pebs()Peter Zijlstra2020-11-091-1/+1
* | perf/core: Add support for PERF_SAMPLE_CODE_PAGE_SIZEStephane Eranian2020-10-291-1/+1
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* perf/x86: Fix n_metric for cancelled txnPeter Zijlstra2020-10-061-0/+1
* perf/x86: Fix n_pair for cancelled txnPeter Zijlstra2020-10-061-0/+1
* perf/x86/intel: Support TopDown metrics on Ice LakeKan Liang2020-08-181-0/+13
* perf/x86/intel: Generic support for hardware TopDown metricsKan Liang2020-08-181-0/+37
* perf/x86/intel: Fix the name of perf METRICSKan Liang2020-08-181-1/+1
* perf/x86/intel/lbr: Support XSAVES for arch LBR readKan Liang2020-07-081-0/+7
* perf/x86/intel/lbr: Support XSAVES/XRSTORS for LBR context switchKan Liang2020-07-081-0/+21
* perf/x86/intel/lbr: Support Architectural LBRKan Liang2020-07-081-0/+10
* perf/x86/intel/lbr: Factor out rdlbr_all() and wrlbr_all()Kan Liang2020-07-081-1/+1
* perf/x86/intel/lbr: Unify the stored format of LBR informationKan Liang2020-07-081-4/+2
* perf/x86/intel/lbr: Support LBR_CTLKan Liang2020-07-081-3/+12
* perf/x86: Expose CPUID enumeration bits for arch LBRKan Liang2020-07-081-0/+13
* perf/x86/intel/lbr: Use dynamic data structure for task_ctxKan Liang2020-07-081-1/+6
* perf/x86/intel/lbr: Factor out a new struct for generic optimizationKan Liang2020-07-081-3/+7
* perf/x86/intel/lbr: Add the function pointers for LBR save and restoreKan Liang2020-07-081-0/+6
* perf/x86/intel/lbr: Add a function pointer for LBR readKan Liang2020-07-081-0/+5
* perf/x86/intel/lbr: Add a function pointer for LBR resetKan Liang2020-07-081-0/+17
* perf/x86: Keep LBR records unchanged in host context for guest usageLike Xu2020-07-021-0/+3
* perf/x86: Add constraint to create guest LBR event without hw counterLike Xu2020-07-021-0/+1
* perf/x86: Fix variable types for LBR registersWei Wang2020-07-021-2/+2
* x86/perf: Add hardware performance events support for Zhaoxin CPU.CodyYao-oc2020-04-301-0/+10
* perf/x86/amd: Add support for Large Increment per Cycle EventsKim Phillips2020-01-171-0/+18
* perf/x86/amd: Constrain Large Increment per Cycle eventsKim Phillips2020-01-171-0/+2
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