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* MIPS: pci-ar71xx: remove static PCI IO/MEM resourcesGabor Juhos2013-02-172-17/+35
| | | | | | Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4927/ Signed-off-by: John Crispin <blogic@openwrt.org>
* MIPS: pci-ar71xx: use dynamically allocated PCI controller structureGabor Juhos2013-02-171-31/+53
| | | | | | Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4926/ Signed-off-by: John Crispin <blogic@openwrt.org>
* MIPS: pci-ar724x: setup command register of the PCI controllerGabor Juhos2013-02-173-1/+74
| | | | | | | | | | | | | | The command register of the PCI controller is not initialized correctly by the bootloader on some boards and this leads to non working PCI bus. Add code to initialize the command register from the Linux code to avoid this. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4916/ Signed-off-by: John Crispin <blogic@openwrt.org>
* MIPS: pci-ar724x: use per-controller IRQ baseGabor Juhos2013-02-171-10/+21
| | | | | | | | | Change to the code to use per-controller IRQ base. This is needed for multiple PCI controller support. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4915/ Signed-off-by: John Crispin <blogic@openwrt.org>
* MIPS: pci-ar724x: remove static PCI IO/MEM resourcesGabor Juhos2013-02-172-17/+44
| | | | | | | | | | | | Static resources become impractical when multiple PCI controllers are present. Move the resources into the platform device registration code and change the probe routine to get those from there platform device's resources. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4914/ Signed-off-by: John Crispin <blogic@openwrt.org>
* MIPS: pci-ar724x: use dynamically allocated PCI controller structureGabor Juhos2013-02-171-47/+82
| | | | | | | | | | | | | | | The current code uses static variables to store the PCI controller specific data. This works if the system contains one PCI controller only, however it becomes impractical when multiple PCI controllers are present. Move the variables into a dynamically allocated controller specific structure, and use that instead of the static variables. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4912/ Signed-off-by: John Crispin <blogic@openwrt.org>
* MIPS: ath79: allow to specify bus number in PCI IRQ mapsGabor Juhos2013-02-172-1/+4
| | | | | | | | This is needed for multiple PCI bus support. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4913/ Signed-off-by: John Crispin <blogic@openwrt.org>
* MIPS: add dummy pci_load_of_rangesGabor Juhos2013-02-171-0/+5
| | | | | | | | | | | | The pci_load_of_ranges function is only available if CONFIG_OF is selected. If the function is used without CONFIG_OF being enabled it will cause a build error. Add a dummy inline function to avoid this. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4911/ Signed-off-by: John Crispin <blogic@openwrt.org>
* MIPS: avoid possible resource conflict in register_pci_controllerGabor Juhos2013-02-171-2/+13
| | | | | | | | | | | | | | | | | | The IO and memory resources of a PCI controller might already have a parent resource set when they are passed to 'register_pci_controller'. If the parent resource is set, the request_resource call will fail due to resource conflict and the current code will not be able to register the PCI controller. Use the parent resource if it is available in the request_resource call to avoid the isssue. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4910/ Signed-off-by: John Crispin <blogic@openwrt.org>
* MIPS: ath79: remove unused ar7{1x,24}x_pcibios_init functionsGabor Juhos2013-02-174-87/+0
| | | | | | | | The functions are unused now, so remove them. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4909/ Signed-off-by: John Crispin <blogic@openwrt.org>
* MIPS: ath79: register platform devices for the PCI controllersGabor Juhos2013-02-171-9/+78
| | | | | | | | | | | The pci-ar71xx and pci-ar724x drivers were converted into platform drivers. Register the corresponding platform devices for the PCI controllers instead of using the ar7{1x,24}x_pcibios_init functions. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4908/ Signed-off-by: John Crispin <blogic@openwrt.org>
* MIPS: ath79: move global PCI defines into a common headerGabor Juhos2013-02-173-24/+24
| | | | | | | | The constants will be used by a subsequent patch. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4907/ Signed-off-by: John Crispin <blogic@openwrt.org>
* MIPS: pci-ar71xx: convert into a platform driverGabor Juhos2013-02-171-4/+56
| | | | | | | | | | The patch converts the pci-ar71xx driver into a platform driver. This makes it possible to register the PCI controller as a plain platform device. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4906/ Signed-off-by: John Crispin <blogic@openwrt.org>
* MIPS: pci-ar724x: convert into a platform driverGabor Juhos2013-02-171-2/+55
| | | | | | | | | | The patch converts the pci-ar724x driver into a platform driver. This makes it possible to register the PCI controller as a plain platform device. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4905/ Signed-off-by: John Crispin <blogic@openwrt.org>
* MIPS: ralink: add CPU interrupt controller to of_irq_idsGabor Juhos2013-02-172-3/+17
| | | | | | | | | | Convert the ralink IRQ code to make use of the new MIPS IRQ controller OF mappings. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Signed-off-by: John Crispin <blogic@openwrt.org> Acked-by: David Daney <david.daney@cavium.com> Patchwork: http://patchwork.linux-mips.org/patch/4900/
* MIPS: add irqdomain support for the CPU IRQ controllerGabor Juhos2013-02-172-0/+48
| | | | | | | | | | Add code to load a irq_domain for the MIPS IRQ controller from a devicetree file. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Signed-off-by: John Crispin <blogic@openwrt.org> Acked-by: David Daney <david.daney@cavium.com> Patchwork: http://patchwork.linux-mips.org/patch/4902/
* MIPS: ralink: adds default config fileJohn Crispin2013-02-171-0/+167
| | | | Signed-off-by: John Crispin <blogic@openwrt.org>
* MIPS: ralink: adds Kbuild filesJohn Crispin2013-02-176-0/+76
| | | | | | | | | Add the Kbuild symbols and Makefiles needed to actually build the ralink code from this series Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4899/
* MIPS: ralink: adds rt305x devicetreeJohn Crispin2013-02-172-0/+148
| | | | | | | | This adds the devicetree file that describes the rt305x evaluation kit. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4898/
* MIPS: ralink: adds support for RT305x SoC familyJohn Crispin2013-02-172-0/+381
| | | | | | | | | | Add support code for rt3050, rt3052, rt3350, rt3352 and rt5350 SOC. The code detects the SoC and registers the clk / pinmux settings. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4896/
* MIPS: ralink: adds early_printk supportJohn Crispin2013-02-171-0/+44
| | | | | | | | Add the code needed to make early printk work. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4897/
* MIPS: ralink: adds OF codeJohn Crispin2013-02-171-0/+107
| | | | | | | | | | Until there is a generic MIPS way of handing the DTB over from bootloader to kernel we rely on a built in devicetrees. The OF code also remaps those register ranges that we use global in our drivers. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4895/
* MIPS: ralink: adds clkdev codeJohn Crispin2013-02-171-0/+72
| | | | | | | | | These SoCs have a limited number of fixed rate clocks. Add support for the clk and clkdev api. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4894/
* MIPS: ralink: adds prom and cmdline codeJohn Crispin2013-02-171-0/+69
| | | | | | | | Add minimal code to handle commandlines. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4892/
* MIPS: ralink: adds reset codeJohn Crispin2013-02-171-0/+44
| | | | | | | | Resetting these SoCs requires no real magic. The code is straight forward. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4891/
* MIPS: ralink: adds irq codeJohn Crispin2013-02-171-0/+176
| | | | | | | | | All of the Ralink Wifi SoC currently supported by this series share the same interrupt controller (INTC). Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4890/
* MIPS: ralink: adds include filesJohn Crispin2013-02-173-0/+108
| | | | | | | | Before we start adding the platform code we add the common include files. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4893/
* MIPS: ath79: simplify MISC IRQ handlingGabor Juhos2013-02-172-36/+10
| | | | | | | | | | | | | | | The current code uses multiple if statements for demultiplexing the different interrupt sources. Additionally, the MISC interrupt controller has 32 interrupt sources and the current code does not handles all of them. Get rid of the if statements and process all interrupt sources in a loop to fix these issues. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4874/ Signed-off-by: John Crispin <blogic@openwrt.org>
* MIPS: ath79: simplify ath79_gpio_function_* routinesGabor Juhos2013-02-171-24/+6
| | | | | | | | | Make ath79_gpio_function_{en,dis}able to be wrappers around ath79_gpio_function_setup. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4871/ Signed-off-by: John Crispin <blogic@openwrt.org>
* MIPS: ath79: fix GPIO function selection for AR934x SoCsGabor Juhos2013-02-172-12/+28
| | | | | | | | | | | | | | GPIO function selection is not working on the AR934x SoCs because the offset of the function selection register is different on those. Add a helper routine which returns the correct register address based on the SoC type, and use that in the 'ath79_gpio_function_*' routines. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4870/ Signed-off-by: John Crispin <blogic@openwrt.org>
* MIPS: Add new GIC clocksource.Steven J. Hill2013-02-176-34/+106
| | | | | | | | | Add new clocksource that uses the counter present on the MIPS Global Interrupt Controller. Signed-off-by: Steven J. Hill <sjhill@mips.com> Patchwork: http://patchwork.linux-mips.org/patch/4681/ Signed-off-by: John Crispin <blogic@openwrt.org>
* MIPS: dsp: Simplify the DSP macros.Steven J. Hill2013-02-171-201/+30
| | | | | | | | | Simplify the DSP macros for vanilla (non-microMIPS) kernels and toolchains that do not support the DSP ASEs. Signed-off-by: Steven J. Hill <sjhill@mips.com> Patchwork: http://patchwork.linux-mips.org/patch/4687/ Signed-off-by: John Crispin <blogic@openwrt.org>
* MIPS: dsp: Support toolchains without DSP ASE and microMIPS.Steven J. Hill2013-02-171-0/+89
| | | | | | | | | Add macros to support the DSP ASE with microMIPS kernels when the toolchain does not have support. Signed-off-by: Steven J. Hill <sjhill@mips.com> Patchwork: http://patchwork.linux-mips.org/patch/4686/ Signed-off-by: John Crispin <blogic@openwrt.org>
* MIPS: dsp: Add assembler support for DSP ASEs.Steven J. Hill2013-02-172-17/+67
| | | | | | | | | | | Newer toolchains support the DSP and DSP Rev2 instructions. This patch performs a check for that support and adds compiler and assembler flags for only the files that need use those instructions. Signed-off-by: Steven J. Hill <sjhill@mips.com> Acked-by: Florian Fainelli <florian@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4752/ Signed-off-by: John Crispin <blogic@openwrt.org>
* MIPS: Add support for the M14KEc core.Steven J. Hill2013-02-179-0/+22
| | | | | | Signed-off-by: Steven J. Hill <sjhill@mips.com> Patchwork: http://patchwork.linux-mips.org/patch/4682/ Signed-off-by: John Crispin <blogic@openwrt.org>
* MIPS: Clean-ups for MIPS Technologies Inc. generic header file.Steven J. Hill2013-02-171-21/+7
| | | | | | | | Clean up standard header text and remove unused #define. Signed-off-by: Steven J. Hill <sjhill@mips.com> Patchwork: http://patchwork.linux-mips.org/patch/4703/ Signed-off-by: John Crispin <blogic@openwrt.org>
* MIPS: PCI: Multi-node PCI support for Netlogic XLPJayachandran C2013-02-171-43/+66
| | | | | | | | | On a multi-chip XLP board, each node can have 4 PCIe links. Update XLP PCI code to initialize PCIe on all the nodes. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Patchwork: http://patchwork.linux-mips.org/patch/4803/ Signed-off-by: John Crispin <blogic@openwrt.org>
* MIPS: Netlogic: Fix for quad-XLP bootJayachandran C2013-02-171-10/+25
| | | | | | | | | | | | | On multi-chip boards, the first core on slave SoCs may take much more time to wakeup. Add code to wait for the core to come up before proceeding with the rest of the boot up. Update xlp_wakeup_core to also skip the boot node and the boot CPU initialization which is already complete. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Patchwork: http://patchwork.linux-mips.org/patch/4783/ Signed-off-by: John Crispin <blogic@openwrt.org>
* MIPS: Netlogic: use preset loops per jiffyJayachandran C2013-02-171-0/+4
| | | | | | | | | | | | | Doing calibrate delay on a hardware thread will be inaccurate since it depends on the load on other threads in the core. It will also slow down the boot process when done for 128 hardware threads. Switch to a pre-computed loops per jiffy based on the core frequency. The value is computed based on the core frequency and roughly matches the value calculated by calibrate_delay(). Signed-off-by: Jayachandran C <jchandra@broadcom.com> Patchwork: http://patchwork.linux-mips.org/patch/4791/ Signed-off-by: John Crispin <blogic@openwrt.org>
* MIPS: Netlogic: No hazards needed for XLR/XLSJayachandran C2013-02-171-1/+1
| | | | | | | | | | TLB and COP0 hazards are handled in hardware for Netlogic XLR/XLS SoCs. Update hazards.h to pick more optimal set of definitions when compiling for XLR/XLS. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Patchwork: http://patchwork.linux-mips.org/patch/4788/ Signed-off-by: John Crispin <blogic@openwrt.org>
* MIPS: PCI: Prevent hang on XLP reg readJayachandran C2013-02-171-1/+5
| | | | | | | | | | Reading PCI extended register at 0x255 on a bridge will hang if there is no device connected on the link. Make PCI read routine skip this register. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Patchwork: http://patchwork.linux-mips.org/patch/4789/ Signed-off-by: John Crispin <blogic@openwrt.org>
* MIPS: Netlogic: Use PIC timer as a clocksourceJayachandran C2013-02-176-8/+110
| | | | | | | | | | | | | | | | | The XLR/XLS/XLP PIC has a 8 countdown timers which run at the PIC frequencey. One of these can be used as a clocksource to provide timestamps that is common across cores. This can be used in place of the count/compare clocksource which is per-CPU. On XLR/XLS PIC registers are 32-bit, so we just use the lower 32-bits of the PIC counter. On XLP, the whole 64-bit can be used. Provide common macros and functions for PIC timer registers on XLR/XLS and XLP, and use them to register a PIC clocksource. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Patchwork: http://patchwork.linux-mips.org/patch/4786/ Signed-off-by: John Crispin <blogic@openwrt.org>
* MIPS: Netlogic: Split XLP L1 i-cache among threadsJayachandran C2013-02-172-0/+8
| | | | | | | | | | | | Since we now use r4k cache code for Netlogic XLP, it is better to split L1 icache among the active threads, so that threads won't step on each other while flushing icache. The L1 dcache is already split among the threads in the core. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Patchwork: http://patchwork.linux-mips.org/patch/4787/ Signed-off-by: John Crispin <blogic@openwrt.org>
* MIPS: PCI: Byteswap not needed in little-endian modeJayachandran C2013-02-171-3/+12
| | | | | | | | | | | | Rename function xlp_enable_pci_bswap() to xlp_config_pci_bswap(), which is a better description for its functionality. When compiled in big-endian mode, xlp_config_pci_bswap() will configure the PCIe links to byteswap. In little-endian mode, no swap configuration is needed for the PCIe controller, and the function is empty. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Patchwork: http://patchwork.linux-mips.org/patch/4802/ Signed-off-by: John Crispin <blogic@openwrt.org>
* MIPS: Netlogic: Optimize EIMR/EIRR accesses in 32-bitJayachandran C2013-02-173-28/+98
| | | | | | | | | | | | | | | | | | | Provide functions ack_c0_eirr(), set_c0_eimr(), clear_c0_eimr() and read_c0_eirr_and_eimr() that do the EIMR and EIRR operations and update the interrupt handling code to use these functions. Also, use the EIMR register functions to mask interrupts in the irq code. The 64-bit interrupt request and mask registers (EIRR and EIMR) are accessed when the interrupts are off, and the common operations are to set or clear a bit in these registers. Using the 64-bit c0 access functions for these operations is not optimal in 32-bit, because it will disable/restore interrupts and split/join the 64-bit value during each register access. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Patchwork: http://patchwork.linux-mips.org/patch/4790/ Signed-off-by: John Crispin <blogic@openwrt.org>
* MIPS: Netlogic: add XLS6xx to FMN configJayachandran C2013-02-171-0/+2
| | | | | | | | | Add support for XLS6xx CPUs to the Fast Message Network (FMN) configuration. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Patchwork: http://patchwork.linux-mips.org/patch/4785/ Signed-off-by: John Crispin <blogic@openwrt.org>
* MIPS: lantiq: rework external irq codeJohn Crispin2013-02-172-32/+74
| | | | | | | | | This code makes the irqs used by the EIU loadable from the DT. Additionally we add a helper that allows the pinctrl layer to map external irqs to real irq numbers. Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4818/
* MIPS: lantiq: improve pci reset gpio handlingJohn Crispin2013-02-171-2/+10
| | | | | | | | We need to make sure that the reset gpio is available and also set a sane default state. Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4817/
* MIPS: lantiq: add GPHY clock gate bitsJohn Crispin2013-02-172-0/+10
| | | | | | | Explicitly enable the clock gate of the internal GPHYs found on xrx200. Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4816/
* MIPS: lantiq: adds static clock for PP32John Crispin2013-02-176-10/+69
| | | | | | | | The Lantiq DSL SoCs have an internal networking processor. Add code to read the static clock rate. Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4815/
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