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* ARM: shmobile: Break out R-Car Gen2 setup codeMagnus Damm2013-10-088-74/+106
| | | | | | | | | | | | | Move arch timer workaround code and boot mode pin handling from setup-r8a7790.c to setup-rcar-gen2.c. With this in place the same code can be used on other R-Car Generation 2 devices such as r8a7791. Signed-off-by: Magnus Damm <damm@opensource.se> [horms+renesas@verge.net.au trivial rebase of board-lager.c for introduction of lager_add_standard_devices()] Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
* ARM: shmobile: r8a73a4: add a clock alias for the DMAC in DT modeGuennadi Liakhovetski2013-10-081-0/+1
| | | | | | | | | Devices, initialised from the Device Tree and from platform code usually have different names. This patch adds a clock alias for DMAC on r8a73a4 in DT mode. Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas@gmail.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
* ARM: shmobile: r8a7790: add I2C clocks and aliases for the DT modeGuennadi Liakhovetski2013-10-081-0/+10
| | | | | | | | This patch adds clock definitions for the 4 I2C interfaces on r8a7790 and clock aliases, suitable for the DT mode. Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas@gmail.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
* ARM: shmobile: r8a7779: add HPB-DMAC supportMax Filippov2013-10-082-0/+161
| | | | | | | | | | | | | | | | | Add HPB-DMAC platform device on R8A7779 SoC along with its slave and channel configurations (only for SDHI0 so far). Signed-off-by: Max Filippov <max.filippov@cogentembedded.com> [Sergei: moved *enum* declaring HPB-DMAC slave IDs from now removed <mach/dma.h> to <mach/r8a7779.h>, removed #include <mach/dma.h> from setup-r8a7779.c, removed SSI-related *enum* values and SSI-related data from hpb_dmae_slaves[] and hpb_dmae_channels[], added ASYNCMDR.ASBTMD{20|24|43} and ASYNCMDR.ASMD{20|24|43} fields/values, fixed comments to ASYNCMDR.ASBTMD2[123] and ASYNCMDR.ASMD2[123] fields/values, renamed all the bit/field/value #define's to include 'HBP_DMAE_' prefix to match the driver, moved comments after the element initializers of hpb_dmae_channels[].] Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
* ARM: shmobile: r8a7778: add HPB-DMAC supportMax Filippov2013-10-082-0/+93
| | | | | | | | | | | | | | Add HPB-DMAC platform device on R8A7778 SoC along with its slave and channel configurations (only for SDHI0 so far). Signed-off-by: Max Filippov <max.filippov@cogentembedded.com> [Sergei: moved *enum* declaring HPB-DMAC slave IDs from now removed <mach/dma.h> to <mach/r8a7778.h>, removed #include <mach/dma.h> from setup-r8a7778.c, removed SSI-related *enum* values and SSI-related data from hpb_dmae_slaves[] and hpb_dmae_channels[], moved the comments after the element initializers of hpb_dmae_channels[].] Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
* ARM: shmobile: r8a73a4: add a DMAC platform device and clock for itGuennadi Liakhovetski2013-10-083-1/+103
| | | | | | | Add a DMAC platform device and clock definitions for it on r8a73a4. Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas@gmail.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
* Merge tag 'renesas-fixes4-for-v3.12' into soc2-baseSimon Horman2013-10-087-16/+38
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fourth Round of Renesas ARM based SoC fixes for v3.12 * Remove unused #gpio-ranges-cells DT property * Remove usage of deprecated #gpio-range-cells DT property from GPIO R-Car Property was deprecated in v3.11-rc2 * Correct ether pinctl naming for armadillo800eva board Regression introduced in v3.10-rc5 * Add Micrel KSZ8041 PHY fixup to lager board This resolves a problem that has been present since 3.11-rc2 * Update SDHI DT compatibility string to the <unit>-<soc> format This makes compatibility strings consistent across all renesas hardware which currently supports DT. The bindings which are being updated where intorodiced on a per-SoC basis starting in v3.8-rc7. They may have been internally consistent when originally added.
| * ARM: shmobile: Remove #gpio-ranges-cells DT propertyLaurent Pinchart2013-09-223-3/+0
| | | | | | | | | | | | | | This property is no longer required by the GPIO binding. Remove it. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| * ARM: shmobile: armadillo: fixup ether pinctrl namingKuninori Morimoto2013-09-221-2/+2
| | | | | | | | | | | | | | | | | | | | e5c9b4cd665106d9b5397114ea81a53059410b6a ("sh_eth: get R8A7740 support out of #ifdef") exchanged sh-eth driver name to r8a7740-gether, but, eva_pinctrl_map[] didn't follow it. Fixes it. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| * ARM: shmobile: Lager: add Micrel KSZ8041 PHY fixupSergei Shtylyov2013-09-211-1/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently on the Lager board NFS timeouts/delays are seen when booting. That turned out to happen because the SoC's ETH_LINK signal turns on and off after each packet. It is connected to Micrel KSZ8041 PHY's LED0 signal. Ether LEDs on the Lager board are named LINK and ACTIVE which corresponds to non-default 01 setting of the PHY control register 1 bits 14-15. The 'sh_eth' driver resets the PHY when opening the network device, so we have to set the mentioned bits back to 01 from the default 00 value which causes bouncing of ETH_LINK. That can be achieved using the PHY platform fixup mechanism if we also modify the driver to use it.. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| * ARM: shmobile: update SDHI DT compatibility string to the <unit>-<soc> formatGuennadi Liakhovetski2013-09-213-10/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | Currently DT compatibility strings of both types can be found in the kernel sources: <unit>-<soc> and <soc>-<unit>, whereas a unique format should be followed and the former one is preferred. This patch converts the SDHI MMC driver and its users to the common standard. This is safe for now, since ATM no real products are using this driver with DT. Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas@gmail.com> Acked-by: Chris Ball <cjb@laptop.org> [Removed r8a7740.dtsi portion as it is not applicable] Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
* | Merge tag 'renesas-smp-for-v3.13' into soc2-baseSimon Horman2013-10-0818-68/+331
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Renesas ARM based SoC SMP updates for v3.13 * Add CPU notifier based SCU boot vector code - Use on emev2, r8a7779 and sh73a0 SoCs - Remove now unused shmobile_smp_scu_boot_secondary() * Add shared APMU SMP support code - Use to add SMP support for r8a7790 SoC * Introduce shmobile_boot_size * Expose shmobile_invalidate_start() * Introduce shmobile_smp_cpu_disable() - Use on sh73a0 SoC - Remove now unused shmobile_smp_init_cpus()
| * | ARM: shmobile: Include CA7 cores in APMU tableMagnus Damm2013-09-301-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add information to the shared APMU code regarding the APMU instance used to control the CA7 cores. This can be used on r8a7790 and r8a73a4, but should most likely be converted to DT in the future. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| * | ARM: shmobile: Extend APMU code to allow single cluster onlyMagnus Damm2013-09-301-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Extend the APMU code with a check to only allow boot of CPU cores that sit in the same cluster as CPU0. This makes it possible for people to use the r8a790 CA7 boot mode with CA7-cores only. The default CA15 boot mode will enable CA15 cores only. This is an intentional software limitation to cope with lacking scheduler support. By removing this patch it is possible to run all 8 cores in parallel, but this is not recommended without out of tree scheduler modfications or custom user space code to control the CPU affinitiy. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| * | ARM: shmobile: Remove shmobile_smp_scu_boot_secondary()Magnus Damm2013-09-302-10/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | Remove shmobile_smp_scu_boot_secondary() since it is no longer used. CPU boot vector setup is instead handled by CPU notifiers. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| * | ARM: shmobile: Let r8a7779 rely on SCU CPU notifierMagnus Damm2013-09-301-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | Now when CPU notifiers are used for SCU boot vector setup shmobile_smp_scu_boot_secondary() is no longer needed. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| * | ARM: shmobile: Let EMEV2 rely on SCU CPU notifierMagnus Damm2013-09-301-6/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | Now when CPU notifiers are used for SCU boot vector setup shmobile_smp_scu_boot_secondary() is no longer needed. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| * | ARM: shmobile: Let sh73a0 rely on SCU CPU notifierMagnus Damm2013-09-301-5/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | Now when CPU notifiers are used for SCU boot vector setup shmobile_smp_scu_boot_secondary() is no longer needed. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| * | ARM: shmobile: Add CPU notifier based SCU boot vector codeMagnus Damm2013-09-301-0/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add CPU notifiers for the shared mach-shmobile SCU code to allow removal of the shared SCU boot_secondary code. Regarding notifiers, at CPU_UP_PREPARE time the SMP boot vector is initialized so secondary CPU cores can boot. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| * | ARM: shmobile: Add r8a7790 SMP support using APMU codeMagnus Damm2013-09-306-0/+72
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add r8a7790 SMP support using the shared APMU code. To enable SMP the r8a7790 specific DTS needs to be updated to include CPU cores, and this is happening in a separate patch. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| * | ARM: shmobile: Shared APMU SMP support code without DTMagnus Damm2013-09-302-0/+184
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Introduce shared APMU SMP code for mach-shmobile. Both SMP boot up and CPU Hotplug is supported. This version does not use DT but if needed this will be added as an incremental feature patch. The code is designed around CONFIG_NR_CPUS and should in theory support any number of APMUs, however due to the current DT-less static design only a single APMU is supported. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| * | ARM: shmobile: Introduce shmobile_boot_sizeMagnus Damm2013-09-202-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | Introduce shmobile_boot_size that can be used by future SMP code to determine the size of the boot code that needs to be copied to internal SRAM. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| * | ARM: shmobile: Expose shmobile_invalidate_start()Magnus Damm2013-09-201-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Expose shmobile_invalidate_start() in common.h for mach-shmobile. This function will be used for boot of secondary processors on future non-SCU SMP platforms. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| * | ARM: shmobile: Remove unused shmobile_smp_init_cpus()Magnus Damm2013-09-202-16/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | Remove shmobile_smp_init_cpus() since all SMP platforms in mach-shmobile now rely on DT for CPU core description instead of for instance determining number of cores from the SCU. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| * | ARM: shmobile: Use shmobile_smp_cpu_disable() on sh73a0Magnus Damm2013-09-201-8/+1
| | | | | | | | | | | | | | | | | | | | | | | | Use shmobile_smp_cpu_disable() on sh73a0 since it allows CPU Hotplug of any CPU. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| * | ARM: shmobile: Introduce shmobile_smp_cpu_disable()Magnus Damm2013-09-202-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | Introduce the shared CPU Hotplug function shmobile_smp_cpu_disable() for mach-shmobile. It is useful for the case when all CPUs may be hotplugged, including CPU 0. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| * | ARM: shmobile: r8a7790: Constify platform data and resourcesLaurent Pinchart2013-09-191-10/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Platform data and resources for core devices are kmemdup()ed when the corresponding devices are registered and can thus be declared as const. Do so. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| * | ARM: shmobile: Rename to r8a7790_init_early()Magnus Damm2013-09-194-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | Rename r8a7790_init_delay() into r8a7790_init_early() to make the function name show that more than just delay setup may happen in the future. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| * | ARM: shmobile: Rename to r8a73a4_init_early()Magnus Damm2013-09-194-5/+5
| |/ | | | | | | | | | | | | | | | | Rename r8a73a4_init_delay() into r8a73a4_init_early() to make the function name show that more than just delay setup may happen in the future. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
* | ARM: shmobile: r8a7778: add usb phy power control functionKuninori Morimoto2013-09-302-11/+28
| | | | | | | | | | | | | | | | | | USB phy initialisation function is needed from not only USB Host but also USB Function too. This patch adds usb phy common control function. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
* | ARM: shmobile: r8a7778: add USBHS clockKuninori Morimoto2013-09-301-0/+1
| | | | | | | | | | | | | | This patch adds USBHS clock for renesas_usbhs driver Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
* | ARM: shmobile: r8a7791 CMT supportMagnus Damm2013-09-303-1/+36
| | | | | | | | | | | | | | | | | | | | | | | | Add r8a7791 CMT support via channel 0 of CMT0. At this point the CMT is used for clock event operation, but in the future the arch timer will be the main timer and the CMT will be used for deep sleep wake up only. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au> (cherry picked from commit a7663b88280d00359715817620798e99d54d401c) Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
* | ARM: shmobile: r8a7791 SCIF supportYoshikazu Fujikawa2013-09-303-1/+118
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add SCIF serial port support to the r8a7791 SoC by adding platform devices for SCIFA0 -> SCIFA5 as well as SCIFB0 -> SCIFB2 and SCIF0 -> SCIF5 together with clock bindings. DT device description is excluded at this point since such bindings are still under development. Signed-off-by: Yoshikazu Fujikawa <yoshikazu.fujikawa.ue@renesas.com> Signed-off-by: Ryo Kataoka <ryo.kataoka.wt@renesas.com> [damm@opensource.se: Forward ported to upstream, dropped holes in enum] Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
* | ARM: shmobile: Initial r8a7791 SoC supportHisashi Nakamura2013-09-306-0/+291
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add initial support for the r8a7791 SoC including: - Single Cortex-A15 CPU Core - GIC No static virtual mappings are used, all the components make use of ioremap(). DT_MACHINE_START is still wrapped in CONFIG_USE_OF to match other mach-shmobile code. Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com> Signed-off-by: Ryo Kataoka <ryo.kataoka.wt@renesas.com> [damm@opensource.se: Forward ported to upstream, dropped not-yet-ready code] Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
* | ARM: shmobile: r8a7778: add SSI/SRU clock supportKuninori Morimoto2013-09-191-2/+41
| | | | | | | | | | | | | | Add a platform clock for the r8a7778 SRU/SSI sound. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
* | ARM: shmobile: r8a7790: Add DU and LVDS clocksLaurent Pinchart2013-09-191-1/+11
| | | | | | | | | | | | Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
* | ARM: shmobile: r8a7779: Rename DU device in clock lookups listLaurent Pinchart2013-09-191-1/+1
|/ | | | | | | | | The DU device will be called rcar-du-r8a7779. Rename the clock lookup entry accordingly. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
* Merge branch 'timers/core' of ↵Linus Torvalds2013-09-162-3/+4
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull timer code update from Thomas Gleixner: - armada SoC clocksource overhaul with a trivial merge conflict - Minor improvements to various SoC clocksource drivers * 'timers/core' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: clocksource: armada-370-xp: Add detailed clock requirements in devicetree binding clocksource: armada-370-xp: Get reference fixed-clock by name clocksource: armada-370-xp: Replace WARN_ON with BUG_ON clocksource: armada-370-xp: Fix device-tree binding clocksource: armada-370-xp: Introduce new compatibles clocksource: armada-370-xp: Use CLOCKSOURCE_OF_DECLARE clocksource: armada-370-xp: Simplify TIMER_CTRL register access clocksource: armada-370-xp: Use BIT() ARM: timer-sp: Set dynamic irq affinity ARM: nomadik: add dynamic irq flag to the timer clocksource: sh_cmt: 32-bit control register support clocksource: em_sti: Convert to devm_* managed helpers
| * clocksource: armada-370-xp: Use CLOCKSOURCE_OF_DECLAREEzequiel Garcia2013-09-021-2/+2
| | | | | | | | | | | | | | | | | | | | This is almost cosmetic: we achieve a bit of consistency with other clocksource drivers by using the CLOCKSOURCE_OF_DECLARE macro for the boilerplate code. Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Reviewed-by: Andrew Lunn <andrew@lunn.ch>
| * ARM: timer-sp: Set dynamic irq affinityViresh Kumar2013-08-221-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When a cpu goes to a deep idle state where its local timer is shutdown, it notifies the time frame work to use the broadcast timer instead. Unfortunately, the broadcast device could wake up any CPU, including an idle one which is not concerned by the wake up at all. This implies, in the worst case, an idle CPU will wake up to send an IPI to another idle cpu. This patch fixes this for ARM platforms using timer-sp, by setting CLOCK_EVT_FEAT_DYNIRQ feature. Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
* | Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linusLinus Torvalds2013-09-156-8/+49
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull MIPS fixes from Ralf Baechle: "These are four patches for three construction sites: - Fix register decoding for the combination of multi-core processors and multi-threading. - Two more fixes that are part of the ongoing DECstation resurrection work. One of these touches a DECstation-only network driver. - Finally Markos' trivial build fix for the AP/SP support. (With this applied now all MIPS defconfigs are building again)" * 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: MIPS: kernel: vpe: Make vpe_attrs an array of pointers. MIPS: Fix SMP core calculations when using MT support. MIPS: DECstation I/O ASIC DMA interrupt handling fix MIPS: DECstation HRT initialization rearrangement
| * | MIPS: kernel: vpe: Make vpe_attrs an array of pointers.Markos Chandras2013-09-131-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 567b21e973ccf5b0d13776e408d7c67099749eb8 "mips: convert vpe_class to use dev_groups" broke the build on MIPS since vpe_attrs should be an array of 'struct device_attribute' pointers. Fixes the following build problem: arch/mips/kernel/vpe.c:1372:2: error: missing braces around initializer [-Werror=missing-braces] arch/mips/kernel/vpe.c:1372:2: error: (near initialization for 'vpe_attrs[0]') [-Werror=missing-braces] Cc: Ralf Baechle <ralf@linux-mips.org> Cc: John Crispin <blogic@openwrt.org> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5819/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: Fix SMP core calculations when using MT support.Leonid Yegoshin2013-09-131-2/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The TCBIND register is only available if the core has MT support. It should not be read otherwise. Secondly, the number of TCs (siblings) are calculated differently depending on if the kernel is configured as SMVP or SMTC. Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5822/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: DECstation I/O ASIC DMA interrupt handling fixMaciej W. Rozycki2013-09-132-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change complements commit d0da7c002f7b2a93582187a9e3f73891a01d8ee4 and brings clear_ioasic_irq back, renaming it to clear_ioasic_dma_irq at the same time, to make I/O ASIC DMA interrupts functional. Unlike ordinary I/O ASIC interrupts DMA interrupts need to be deasserted by software by writing 0 to the respective bit in I/O ASIC's System Interrupt Register (SIR), similarly to how CP0.Cause.IP0 and CP0.Cause.IP1 bits are handled in the CPU (the difference is SIR DMA interrupt bits are R/W0C so there's no need for an RMW cycle). Otherwise the handler is reentered over and over again. The only current user is the DEC LANCE Ethernet driver and its extremely uncommon DMA memory error handler that does not care when exactly the interrupt is cleared. Anticipating the use of DMA interrupts by the Zilog SCC driver this change however exports clear_ioasic_dma_irq for device drivers to choose the right application-specific sequence to clear the request explicitly rather than calling it implicitly in the .irq_eoi handler of `struct irq_chip'. Previously these interrupts were cleared in the .end handler of the said structure, before it was removed. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5826/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: DECstation HRT initialization rearrangementMaciej W. Rozycki2013-09-133-5/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Not all I/O ASIC versions have the free-running counter implemented, an early revision used in the 5000/1xx models aka 3MIN and 4MIN did not have it. Therefore we cannot unconditionally use it as a clock source. Fortunately if not implemented its register slot has a fixed value so it is enough if we check for the value at the end of the calibration period being the same as at the beginning. This also means we need to look for another high-precision clock source on the systems affected. The 5000/1xx can have an R4000SC processor installed where the CP0 Count register can be used as a clock source. Unfortunately all the R4k DECstations suffer from the missed timer interrupt on CP0 Count reads erratum, so we cannot use the CP0 timer as a clock source and a clock event both at a time. However we never need an R4k clock event device because all DECstations have a DS1287A RTC chip whose periodic interrupt can be used as a clock source. This gives us the following four configuration possibilities for I/O ASIC DECstations: 1. No I/O ASIC counter and no CP0 timer, e.g. R3k 5000/1xx (3MIN). 2. No I/O ASIC counter but the CP0 timer, i.e. R4k 5000/150 (4MIN). 3. The I/O ASIC counter but no CP0 timer, e.g. R3k 5000/240 (3MAX+). 4. The I/O ASIC counter and the CP0 timer, e.g. R4k 5000/260 (4MAX+). For #1 and #2 this change stops the I/O ASIC free-running counter from being installed as a clock source of a 0Hz frequency. For #2 it also arranges for the CP0 timer to be used as a clock source rather than a clock event device, because having an accurate wall clock is more important than a high-precision interval timer. For #3 there is no change. For #4 the change makes the I/O ASIC free-running counter installed as a clock source so that the CP0 timer can be used as a clock event device. Unfortunately the use of the CP0 timer as a clock event device relies on a succesful completion of c0_compare_interrupt. That never happens, because while waiting for a CP0 Compare interrupt to happen the function spins in a loop reading the CP0 Count register. This makes the CP0 Count erratum trigger reliably causing the interrupt waited for to be lost in all cases. As a result #4 resorts to using the CP0 timer as a clock source as well, just as #2. However we want to keep this separate arrangement in case (hope) c0_compare_interrupt is eventually rewritten such that it avoids the erratum. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5825/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | | Merge tag 'xtensa-next-20130912' of git://github.com/czankel/xtensa-linuxLinus Torvalds2013-09-1311-353/+324
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull Xtensa updates from Chris Zankel. * tag 'xtensa-next-20130912' of git://github.com/czankel/xtensa-linux: xtensa: Fix broken allmodconfig build xtensa: remove CCOUNT_PER_JIFFY xtensa: fix !CONFIG_XTENSA_CALIBRATE_CCOUNT build failure xtensa: don't use echo -e needlessly xtensa: new fast_alloca handler xtensa: keep a3 and excsave1 on entry to exception handlers xtensa: enable kernel preemption xtensa: check thread flags atomically on return from user exception
| * | | xtensa: Fix broken allmodconfig buildGuenter Roeck2013-09-061-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | xtansa allmodbuild fails with: arch/xtensa/kernel/xtensa_ksyms.c:129:1: error: '_mcount' undeclared here (not in a function) make[2]: *** [arch/xtensa/kernel/xtensa_ksyms.o] Error 1 make[1]: *** [arch/xtensa/kernel] Error 2 The breakage is due to commit 478ba61af (xtensa: add static function tracer support) which exports _mcount without declaring it. Cc: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Chris Zankel <chris@zankel.net>
| * | | xtensa: remove CCOUNT_PER_JIFFYBaruch Siach2013-09-063-5/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use ccount_freq directly to make the code a little more readable. Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Chris Zankel <chris@zankel.net>
| * | | xtensa: fix !CONFIG_XTENSA_CALIBRATE_CCOUNT build failureBaruch Siach2013-09-062-7/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commits 925f5532 (xtensa: ccount based clockevent implementation) and e3f43291 (xtensa: ccount based sched_clock) introduced users of ccount_freq. This variable doesn't exist when CONFIG_XTENSA_CALIBRATE_CCOUNT is disabled. Add ccount_freq definition in this case. Reported-by: Chen Gang <gang.chen@asianux.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Chris Zankel <chris@zankel.net>
| * | | xtensa: don't use echo -e needlesslyMax Filippov2013-09-062-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | -e is not needed to output strings without escape sequences. This breaks big endian FSF build when the shell is dash, because its builtin echo doesn't understand '-e' switch and outputs it in the echoed string. Reported-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Chris Zankel <chris@zankel.net>
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