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| | | | * | clk: samsung: exynos850: Implement CMU_CMGP domainSam Protsenko2021-11-221-0/+100
| | | | * | clk: samsung: exynos850: Implement CMU_APM domainSam Protsenko2021-11-221-1/+141
| | | | * | clk: samsung: Update CPU clk registrationWill McVicker2021-11-206-57/+67
| | | | * | clk: samsung: Remove meaningless __init and extern from header filesSylwester Nawrocki2021-11-192-18/+18
| | | | * | clk: samsung: remove __clk_lookup() usageMarek Szyprowski2021-11-198-36/+32
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| | | * | clk: imx8mp: Fix the parent clk of the audio_root_clkHui Wang2021-11-221-1/+1
| | | * | clk: imx8mn: Fix imx8mn_clko1_selsAdam Ford2021-11-221-3/+3
| | | * | clk: imx: Use div64_ul instead of do_divChangcheng Deng2021-11-221-3/+3
| | | * | clk: imx: imx8ulp: set suppress_bind_attrs to truePeng Fan2021-11-221-0/+1
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| | * | clk: tegra: Support runtime PM and power domainDmitry Osipenko2021-12-158-54/+420
| | * | clk: tegra: Make vde a child of pll_p on tegra114Dmitry Osipenko2021-12-151-1/+1
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| *-----. \ Merge branches 'clk-x86', 'clk-stm', 'clk-amlogic' and 'clk-allwinner' into c...Stephen Boyd2022-01-1150-259/+2602
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| | | | | * | clk: sunxi-ng: Add support for the D1 SoC clocksSamuel Holland2021-11-236-0/+1576
| | | | | * | clk: sunxi-ng: gate: Add macros for gates with fixed dividersSamuel Holland2021-11-231-1/+31
| | | | | * | clk: sunxi-ng: mux: Add macros using clk_parent_data and clk_hwSamuel Holland2021-11-231-0/+33
| | | | | * | clk: sunxi-ng: mp: Add macros using clk_parent_data and clk_hwSamuel Holland2021-11-231-0/+49
| | | | | * | clk: sunxi-ng: div: Add macros using clk_parent_data and clk_hwSamuel Holland2021-11-231-0/+78
| | | | | * | clk: sunxi-ng: Allow the CCU core to be built as a moduleSamuel Holland2021-11-234-17/+24
| | | | | * | clk: sunxi-ng: Convert early providers to platform driversSamuel Holland2021-11-2311-173/+333
| | | | | * | clk: sunxi-ng: Allow drivers to be built as modulesSamuel Holland2021-11-2212-47/+98
| | | | | * | clk: sunxi-ng: Export symbols used by CCU driversSamuel Holland2021-11-2214-0/+35
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| | | | * | clk: meson: gxbb: Fix the SDM_EN bit for MPLL0 on GXBBMartin Blumenstingl2021-11-301-3/+41
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| | | * | clk: stm32: Fix ltdc's clock turn off by clk_disable_unused() after system en...Dillon Min2021-12-151-4/+0
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| | * | clk: x86: Fix clk_gate_flags for RV_CLK_GATEAjit Kumar Pandey2022-01-061-1/+1
| | * | clk: x86: Use dynamic con_id string during clk registrationAjit Kumar Pandey2022-01-061-2/+2
| | * | x86: clk: clk-fch: Add support for newer family of AMD's SOCAjit Kumar Pandey2022-01-061-11/+31
| | * | clk: Introduce clk-tps68470 driverHans de Goede2021-12-153-0/+270
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| *-----. \ Merge branches 'clk-doc', 'clk-renesas', 'clk-at91', 'clk-cleanup' and 'clk-d...Stephen Boyd2022-01-1132-596/+1259
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| | | | | * | clk: Enable/Disable runtime PM for clk_summaryTaniya Das2022-01-051-0/+2
| | | | | * | clk: Emit a stern warning with writable debugfs enabledStephen Boyd2021-12-101-0/+18
| | | | | * | clk: Add write operation for clk_parent debugfs nodeSam Protsenko2021-12-091-1/+41
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| | | | * | clk: stm32mp1: remove redundant assignment to pointer dataColin Ian King2021-12-151-2/+0
| | | | * | clk: __clk_core_init() never takes NULLStephen Boyd2021-12-091-3/+0
| | | | * | clk: clk_core_get() can also return NULLStephen Boyd2021-12-091-7/+8
| | | | * | clk/ti/adpll: Make const pointer error a static const arrayColin Ian King2021-12-091-1/+1
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| | | * | clk: lan966x: Extend lan966x clock driver for clock gating supportHoratiu Vultur2021-12-081-3/+56
| | | * | clk: gate: Add devm_clk_hw_register_gate()Horatiu Vultur2021-12-081-0/+35
| | | * | clk: lan966x: Add lan966x SoC clock driverKavyasree Kotagiri2021-12-083-0/+248
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| | * | clk: renesas: r9a07g044: Add GPU clock and reset entriesBiju Das2021-12-081-0/+9
| | * | clk: renesas: r9a07g044: Add mux and divider for G clockBiju Das2021-12-082-0/+10
| | * | clk: renesas: r9a07g044: Rename CLK_PLL3_DIV4 macroBiju Das2021-12-081-2/+2
| | * | clk: renesas: cpg-mssr: Add support for R-Car S4-8Yoshihiro Shimoda2021-12-085-0/+196
| | * | clk: renesas: rcar-gen4: Introduce R-Car Gen4 CPG driverYoshihiro Shimoda2021-12-087-341/+437
| | * | clk: renesas: r9a07g044: Add TSU clock and reset entryBiju Das2021-11-261-0/+3
| | * | clk: renesas: cpg-mssr: propagate return value of_genpd_add_provider_simple()Lad Prabhakar2021-11-191-2/+1
| | * | clk: renesas: cpg-mssr: Check return value of pm_genpd_init()Lad Prabhakar2021-11-191-1/+14
| | * | clk: renesas: rzg2l: propagate return value of_genpd_add_provider_simple()Lad Prabhakar2021-11-191-2/+1
| | * | clk: renesas: rzg2l: Check return value of pm_genpd_init()Lad Prabhakar2021-11-191-1/+13
| | * | clk: renesas: r9a07g044: Add RSPI clock and reset entriesLad Prabhakar2021-11-191-0/+9
| | * | clk: renesas: r9a07g044: Change core clock "I" from DEF_FIXED->DEF_DIVBiju Das2021-11-191-1/+10
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