summaryrefslogtreecommitdiff
path: root/drivers/clk
Commit message (Expand)AuthorAgeFilesLines
* Merge branch 'renesas-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/g...Stephen Rothwell2022-06-2811-111/+114
|\
| * clk: renesas: r8a779f0: Add HSCIF clocksWolfram Sang2022-06-171-0/+4
| * clk: renesas: r8a779f0: Add PCIe clocksYoshihiro Shimoda2022-06-171-0/+2
| * clk: renesas: r8a779f0: Add Z0 and Z1 clock supportGeert Uytterhoeven2022-06-171-0/+2
| * clk: renesas: rza1: Remove struct rz_cpgGeert Uytterhoeven2022-06-131-18/+15
| * clk: renesas: r8a7779: Remove struct r8a7779_cpgGeert Uytterhoeven2022-06-131-18/+9
| * clk: renesas: r8a7778: Remove struct r8a7778_cpgGeert Uytterhoeven2022-06-131-22/+9
| * clk: renesas: sh73a0: Remove sh73a0_cpg.regGeert Uytterhoeven2022-06-131-13/+13
| * clk: renesas: r8a7740: Remove r8a7740_cpg.regGeert Uytterhoeven2022-06-131-10/+10
| * clk: renesas: r8a73a4: Remove r8a73a4_cpg.regGeert Uytterhoeven2022-06-131-11/+11
| * clk: renesas: r8a779f0: Add SDHI0 clockWolfram Sang2022-06-131-0/+1
| * clk: renesas: r8a779f0: Add thermal clockWolfram Sang2022-06-131-0/+1
| * clk: renesas: rzg2l: Fix reset status functionBiju Das2022-06-071-1/+1
| * clk: renesas: r9a06g032: Fix UART clkgrp bitselRalph Siemsen2022-06-061-4/+4
| * clk: renesas: r9a06g032: Drop some unused fieldsRalph Siemsen2022-06-061-13/+11
| * clk: renesas: r9a09g011: Add WDT clock and reset entriesPhil Edworthy2022-06-061-0/+3
| * clk: renesas: r9a09g011: Add PFC clock and reset entriesPhil Edworthy2022-06-061-0/+2
| * clk: renesas: r9a07g044: Add POEG clock and reset entriesBiju Das2022-06-061-1/+13
| * clk: renesas: r9a07g044: Add GPT clock and reset entryBiju Das2022-06-061-1/+4
* | Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/abel...Stephen Rothwell2022-06-282-18/+24
|\ \
| * | clk: imx: clk-fracn-gppll: Add more freq config for video pllPeng Fan2022-06-161-0/+3
| * | clk: imx: clk-fracn-gppll: correct rdivPeng Fan2022-06-161-1/+2
| * | clk: imx: clk-fracn-gppll: Return rate in rate table properly in ->recalc_rate()Liu Ying2022-06-161-11/+13
| * | clk: imx: clk-fracn-gppll: fix mfd valuePeng Fan2022-06-161-4/+4
| * | clk: imx93: Correct the edma1's parent clockJacky Bai2022-06-161-1/+1
| * | clk: imx93: correct nic_media parentPeng Fan2022-06-161-1/+1
| * | clk: imx93: use adc_root as the parent clock of adc1Haibo Chen2022-06-161-1/+1
| |/
* | Merge branch 'clk-next' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/...Stephen Rothwell2022-06-2829-398/+758
|\ \
| * \ Merge branch 'clk-devm-enable' into clk-nextStephen Boyd2022-06-222-49/+1
| |\ \
| | * | clk: Remove never used devm_clk_*unregister()Andy Shevchenko2022-06-221-48/+0
| | * | clk: Fix pointer casting to prevent oops in devm_clk_release()Uwe Kleine-König2022-06-221-1/+1
| * | | Merge branch 'clk-ti-dt' into clk-nextStephen Boyd2022-06-163-189/+185
| |\ \ \
| | * | | clk: ti: Stop using legacy clkctrl names for omap4 and 5Tony Lindgren2022-06-163-189/+185
| | | |/ | | |/|
| * | | Merge branch 'clk-devm-enable' into clk-nextStephen Boyd2022-06-152-48/+79
| |\ \ \ | | | |/ | | |/|
| | * | clk: meson: axg-audio: Don't duplicate devm_clk_get_enabled()Uwe Kleine-König2022-06-151-32/+4
| | * | clk: Provide new devm_clk helpers for prepared and enabled clocksUwe Kleine-König2022-06-151-0/+27
| | * | clk: generalize devm_clk_get() a bitUwe Kleine-König2022-06-151-17/+49
| | |/
| * | Merge branch 'clk-mtk' into clk-nextStephen Boyd2022-06-1520-82/+492
| |\ \
| | * | clk: mediatek: reset: Add infra_ao reset support for MT8186Rex-BC Chen2022-06-151-0/+23
| | * | clk: mediatek: reset: Add infra_ao reset support for MT8192/MT8195Rex-BC Chen2022-06-154-6/+60
| | * | clk: mediatek: reset: Add reset support for simple probeRex-BC Chen2022-06-152-0/+8
| | * | clk: mediatek: reset: Add new register reset function with deviceRex-BC Chen2022-06-1513-16/+86
| | * | clk: mediatek: reset: Change return type for clock reset register functionRex-BC Chen2022-06-152-8/+13
| | * | clk: mediatek: reset: Support inuput argument index modeRex-BC Chen2022-06-152-1/+25
| | * | clk: mediatek: reset: Support nonsequence base offsets of reset registersRex-BC Chen2022-06-1515-43/+85
| | * | clk: mediatek: reset: Revise structure to control reset registerRex-BC Chen2022-06-1515-40/+186
| | * | clk: mediatek: reset: Merge and revise reset register functionRex-BC Chen2022-06-1515-46/+61
| | * | clk: mediatek: reset: Extract common drivers to update functionRex-BC Chen2022-06-151-16/+22
| | * | clk: mediatek: reset: Refine and reorder functions in reset.cRex-BC Chen2022-06-151-32/+36
| | * | clk: mediatek: reset: Fix written reset bit offsetRex-BC Chen2022-06-151-2/+2
View Lorry Controller Status