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* crypto: tegra - remove driverStephen Warren2014-02-271-1/+0
| | | | | | | | | | | This driver has never been hooked up in any board file, and cannot be instantiated via device tree. I've been told that, at least on Tegra20, the HW is slower at crypto than the main CPU. I have no test-case for it. Hence, remove it. Cc: Varun Wadekar <vwadekar@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: omap-des - Add config and build optionsJoel Fernandes2014-02-271-0/+1
| | | | | | | Add config and build options for the omap-des driver. Signed-off-by: Joel Fernandes <joelf@ti.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: drivers - Sort drivers/crypto/MakefileMarek Vasut2014-01-051-17/+17
| | | | | | | | | | The order in the Makefile was a mess, sort it. Signed-off-by: Marek Vasut <marex@denx.de> Cc: David S. Miller <davem@davemloft.net> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: mxs - Add Freescale MXS DCP driverMarek Vasut2014-01-051-0/+1
| | | | | | | | | | | | | Add support for the MXS DCP block. The driver currently supports SHA-1/SHA-256 hashing and AES-128 CBC/ECB modes. The non-standard CRC32 is not yet supported. Signed-off-by: Marek Vasut <marex@denx.de> Cc: David S. Miller <davem@davemloft.net> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Shawn Guo <shawn.guo@linaro.org> Cc: devicetree@vger.kernel.org Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: mxs - Remove the old DCP driverMarek Vasut2014-01-051-1/+0
| | | | | | | | | | | | | | | | | | | | Remove the old DCP driver as it had multiple severe issues. The driver will be replaced by a more robust implementation. Here is a short list of problems with this driver: 1) It only supports AES_CBC 2) The driver was apparently never ran behind anyone working with MXS. ie.: -> Restarting the DCP block is not done via mxs_reset_block() -> The DT name is not "fsl,dcp" or "fsl,mxs-dcp" as other MXS drivers 3) Introduces new ad-hoc IOCTLs 4) The IRQ handler can't use usual completion() in the driver because that'd trigger "scheduling while atomic" oops, yes? Signed-off-by: Marek Vasut <marex@denx.de> Cc: David S. Miller <davem@davemloft.net> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crytpo: ccp - CCP device driver build filesTom Lendacky2013-12-051-0/+1
| | | | | | | | These files provide the ability to configure and build the AMD CCP device driver and crypto API support. Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: dcp - Added support for Freescale's DCP co-processorTobias Rauter2013-05-281-0/+1
| | | | | | | | | | | | | | | | | | | | | | This patch enables the DCP crypto functionality on imx28. Currently, only aes-128-cbc is supported. Moreover, the dcpboot misc-device, which is used by Freescale's SDK tools and uses a non-software-readable OTP-key, is added. Changes of v2: - ring buffer for hardware-descriptors - use of ablkcipher walk - OTP key encryption/decryption via misc-device (compatible to Freescale-SDK) - overall cleanup The DCP is also capable of sha1/sha256 but I won't be able to add that anytime soon. Tested with built-in runtime-self-test, tcrypt and openssl via cryptodev 1.6 on imx28-evk and a custom built imx28-board. Signed-off-by: Tobias Rauter <tobias.rauter@gmail.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: sahara - Add driver for SAHARA2 accelerator.Javier Martin2013-03-211-0/+1
| | | | | | | | | | | | | SAHARA2 HW module is included in the i.MX27 SoC from Freescale. It is capable of performing cipher algorithms such as AES, 3DES..., hashing and RNG too. This driver provides support for AES-CBC and AES-ECB by now. Reviewed-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Javier Martin <javier.martin@vista-silicon.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: atmel - add Atmel SHA1/SHA256 driverNicolas Royer2012-07-111-0/+1
| | | | | | | | Signed-off-by: Nicolas Royer <nicolas@eukrea.com> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com> Acked-by: Eric Bénard <eric@eukrea.com> Tested-by: Eric Bénard <eric@eukrea.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: atmel - add Atmel DES/TDES driverNicolas Royer2012-07-111-0/+1
| | | | | | | | Signed-off-by: Nicolas Royer <nicolas@eukrea.com> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com> Acked-by: Eric Bénard <eric@eukrea.com> Tested-by: Eric Bénard <eric@eukrea.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: atmel - add Atmel AES driverNicolas Royer2012-07-111-0/+1
| | | | | | | | Signed-off-by: Nicolas Royer <nicolas@eukrea.com> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com> Acked-by: Eric Bénard <eric@eukrea.com> Tested-by: Eric Bénard <eric@eukrea.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: nx - move nx build to driver/crypto MakefileSeth Jennings2012-06-271-0/+1
| | | | | | | | | | | | | When the nx driver was pulled, the Makefile that actually builds it is arch/powerpc/Makefile. This is unnatural. This patch moves the line that builds the nx driver from arch/powerpc/Makefile to drivers/crypto/Makefile where it belongs. Signed-off-by: Seth Jennings <sjenning@linux.vnet.ibm.com> Acked-by: Kent Yoder <key@linux.vnet.ibm.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: bfin_crc - CRC hardware driver for BF60x family processors.Sonic Zhang2012-06-121-1/+2
| | | | | | | | | | | The CRC peripheral is a hardware block used to compute the CRC of the block of data. This is based on a CRC32 engine which computes the CRC value of 32b data words presented to it. For data words of < 32b in size, this driver pack 0 automatically into 32b data units. This driver implements the async hash crypto framework API. Signed-off-by: Sonic Zhang <sonic.zhang@analog.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: ux500 - Add driver for CRYP hardwareAndreas Westin2012-05-041-0/+1
| | | | | | | | | | This adds a driver for the ST-Ericsson ux500 crypto hardware module. It supports AES, DES and 3DES, the driver implements support for AES-ECB,CBC and CTR. Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Andreas Westin <andreas.westin@stericsson.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: driver for Tegra AES hardwareVarun Wadekar2012-01-131-0/+1
| | | | | | | | driver supports ecb/cbc/ofb/ansi_x9.31rng modes, 128, 192 and 256-bit key sizes Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: s5p-sss - add S5PV210 advanced crypto engine supportVladimir Zapolskiy2011-04-081-0/+1
| | | | | | | | This change adds support for AES encrypting and decrypting using advanced crypto engine found on Samsung S5PV210 and S5PC110 SoCs. Signed-off-by: Vladimir Zapolskiy <vzapolskiy@gmail.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: caam - Add support for the Freescale SEC4/CAAMKim Phillips2011-03-271-0/+1
| | | | | | | | | | | | | | | | | | | | | | The SEC4 supercedes the SEC2.x/3.x as Freescale's Integrated Security Engine. Its programming model is incompatible with all prior versions of the SEC (talitos). The SEC4 is also known as the Cryptographic Accelerator and Assurance Module (CAAM); this driver is named caam. This initial submission does not include support for Data Path mode operation - AEAD descriptors are submitted via the job ring interface, while the Queue Interface (QI) is enabled for use by others. Only AEAD algorithms are implemented at this time, for use with IPsec. Many thanks to the Freescale STC team for their contributions to this driver. Signed-off-by: Steve Cornelius <sec@pobox.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: picoxcell - add support for the picoxcell crypto enginesJamie Iles2011-02-211-1/+1
| | | | | | | | Picochip picoXcell devices have two crypto engines, one targeted at IPSEC offload and the other at WCDMA layer 2 ciphering. Signed-off-by: Jamie Iles <jamie@jamieiles.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: Makefile - replace the use of <module>-objs with <module>-yTracey Dent2010-10-191-1/+1
| | | | | | | Changed <module>-objs to <module>-y in Makefile. Signed-off-by: Tracey Dent <tdent48227@gmail.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: omap-aes - OMAP2/3 AES hw accelerator driverDmitry Kasatkin2010-09-031-0/+1
| | | | | Signed-off-by: Dmitry Kasatkin <dmitry.kasatkin@nokia.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: n2 - Add Niagara2 crypto driverDavid S. Miller2010-05-191-0/+2
| | | | | | | | | | | | Current deficiencies: 1) No HMAC hash support yet. 2) Although the algs are registered as ASYNC they always run synchronously. Signed-off-by: David S. Miller <davem@davemloft.net> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: omap - sha1 & md5 driverDmitry Kasatkin2010-05-031-0/+2
| | | | | | | | | | | | | Earlier kernel contained omap sha1 and md5 driver, which was not maintained, was not ported to new crypto APIs and removed from the source tree. - implements async crypto API using dma and cpu. - supports multiple sham instances if available - hmac - concurrent requests Signed-off-by: Dmitry Kasatkin <dmitry.kasatkin@nokia.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: mv_cesa - Add support for Orion5X crypto engineSebastian Andrzej Siewior2009-08-101-0/+1
| | | | | | | | | | This adds support for Marvell's Cryptographic Engines and Security Accelerator (CESA) which can be found on a few SoC. Tested with dm-crypt. Acked-by: Nicolas Pitre <nico@marvell.com> Signed-off-by: Sebastian Andrzej Siewior <sebastian@breakpoint.cc> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: amcc - Add crypt4xx driverJames Hsiao2009-02-181-0/+1
| | | | | | | | | | | This patch adds support for AMCC ppc4xx security device driver. This is the initial release that includes the driver framework with AES and SHA1 algorithms support. The remaining algorithms will be released in the near future. Signed-off-by: James Hsiao <jhsiao@amcc.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: ixp4xx - Hardware crypto support for IXP4xx CPUsChristian Hohnstaedt2008-07-101-0/+1
| | | | | | | | | | | Add support for the hardware crypto engine provided by the NPE C of the Intel IXP4xx networking processor series. Supported ciphers: des, des3, aes and a combination of them with md5 and sha1 hmac Signed-off-by: Christian Hohnstaedt <chohnstaedt@innominate.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: talitos - Freescale integrated security engine (SEC) driverKim Phillips2008-07-101-0/+1
| | | | | | | | | | Add support for the SEC available on a wide range of PowerQUICC devices, e.g. MPC8349E, MPC8548E. This initial version supports authenc(hmac(sha1),cbc(aes)) for use with IPsec. Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* [CRYPTO] hifn_795x: HIFN 795x driverEvgeniy Polyakov2008-01-111-0/+1
| | | | | | | | | | This is a driver for HIFN 795x crypto accelerator chips. It passed all tests for AES, DES and DES3_EDE except weak test for DES, since hardware can not determine weak keys. Signed-off-by: Evgeniy Polyakov <johnpol@2ka.mipt.ru> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* [CRYPTO] padlock: Remove pointless padlock moduleSimon Arlott2007-05-021-1/+0
| | | | | | | | | | | | | | | When this is compiled in it is run too early to do anything useful: [ 6.052000] padlock: No VIA PadLock drivers have been loaded. [ 6.052000] padlock: Using VIA PadLock ACE for AES algorithm. [ 6.052000] padlock: Using VIA PadLock ACE for SHA1/SHA256 algorithms. When it's a module it isn't doing anything special, the same functionality can be provided in userspace by "probeall padlock padlock-aes padlock-sha" in modules.conf if it is required. Signed-off-by: Simon Arlott <simon@fire.lp0.eu> Cc: Michal Ludvig <michal@logix.cz> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* [PATCH] crypto: Add support for the Geode LX AES hardwareJordan Crouse2006-12-061-0/+1
| | | | | | | Add a driver to support the AES hardware on the Geode LX processor. Signed-off-by: Jordan Crouse <jordan.crouse@amd.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* [CRYPTO] padlock: Helper module padlock.koMichal Ludvig2006-09-211-0/+1
| | | | | | | | | | | | Compile a helper module padlock.ko that will try to autoload all configured padlock algorithms. This also provides backward compatibility with the ancient times before padlock.ko was renamed to padlock-aes.ko Signed-off-by: Michal Ludvig <michal@logix.cz> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* [CRYPTO] padlock: Driver for SHA1 / SHA256 algorithmsMichal Ludvig2006-09-211-0/+1
| | | | | | | Support for SHA1 / SHA256 algorithms in VIA C7 processors. Signed-off-by: Michal Ludvig <michal@logix.cz> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* [CRYPTO] padlock: Get rid of padlock-generic.cMichal Ludvig2006-09-211-7/+1
| | | | | | | | | | Merge padlock-generic.c into padlock-aes.c and compile AES as a standalone module. We won't make a monolithic padlock.ko with all supported algorithms, instead we'll compile each driver into its own module. Signed-off-by: Michal Ludvig <michal@logix.cz> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* Linux-2.6.12-rc2v2.6.12-rc2Linus Torvalds2005-04-161-0/+7
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
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