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path: root/drivers/gpu/host1x/mipi.c
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* gpu: host1x: mipi: Use devm_platform_get_and_ioremap_resource()Ye Xingchen2023-04-041-3/+1
| | | | | | | | | Convert platform_get_resource(), devm_ioremap_resource() to a single call to devm_platform_get_and_ioremap_resource(), as this is exactly what this function does. Signed-off-by: Ye Xingchen <ye.xingchen@zte.com.cn> Signed-off-by: Thierry Reding <treding@nvidia.com>
* media: gpu: host1x: mipi: Keep MIPI clock enabled and mutex locked till ↵Sowjanya Komatineni2020-08-281-12/+10
| | | | | | | | | | | | | | | | | | | | | | | | calibration done With the split of MIPI calibration into tegra_mipi_calibrate() and tegra_mipi_wait(), MIPI clock is not kept enabled and mutex is not locked till the calibration is done. So, this patch keeps MIPI clock enabled and mutex locked after triggering start of calibration till its done. To let calibration process go through its finite sequence codes before calibration logic waiting for pads idle state added wait time of 75usec to make sure it sees idle state to apply the results. This patch renames tegra_mipi_calibrate() as tegra_mipi_start_calibration() and tegra_mipi_wait() as tegra_mipi_finish_calibration() to be inline with their usage. Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
* gpu: host1x: mipi: Split tegra_mipi_calibrate() and tegra_mipi_wait()Sowjanya Komatineni2020-07-171-4/+13
| | | | | | | | | | | | | | | | | | | | | | SW can trigger MIPI pads calibration any time after power on but calibration results will be latched and applied to the pads by MIPI CAL unit only when the link is in LP-11 state and then status register will be updated. For CSI, trigger of pads calibration happen during CSI stream enable where CSI receiver is kept ready prior to sensor or CSI transmitter stream start. So, pads may not be in LP-11 at this time and waiting for the calibration to be done immediate after calibration start will result in timeout. This patch splits tegra_mipi_calibrate() and tegra_mipi_wait() so triggering for calibration and waiting for it to complete can happen at different stages. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* gpu: host1x: mipi: Use readl_relaxed_poll_timeout() in tegra_mipi_wait()Sowjanya Komatineni2020-07-171-12/+8
| | | | | | | | Use readl_relaxed_poll_timeout() in tegra_mipi_wait() to simplify the code. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* gpu: host1x: mipi: Update tegra_mipi_request() to be node basedSowjanya Komatineni2020-07-171-2/+2
| | | | | | | | | | | | | Tegra CSI driver need a separate MIPI device for each channel as calibration of corresponding MIPI pads for each channel should happen independently. So, this patch updates tegra_mipi_request() API to add a device_node pointer argument to allow creating mipi device for specific device node rather than a device. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* drm/tegra: dsi: Enhance runtime power managementThierry Reding2016-08-241-32/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The MIPI DSI output on Tegra SoCs requires some external logic to calibrate the MIPI pads before a video signal can be transmitted. This MIPI calibration logic requires to be powered on while the MIPI pads are being used, which is currently done as part of the DSI driver's probe implementation. This is suboptimal because it will leave the MIPI calibration logic powered up even if the DSI output is never used. On Tegra114 and earlier this behaviour also causes the driver to hang while trying to power up the MIPI calibration logic because the power partition that contains the MIPI calibration logic will be powered on by the display controller at output pipeline configuration time. Thus the power up sequence for the MIPI calibration logic happens before it's power partition is guaranteed to be enabled. Fix this by splitting up the API into a request/free pair of functions that manage the runtime dependency between the DSI and the calibration modules (no registers are accessed) and a set of enable, calibrate and disable functions that program the MIPI calibration logic at points in time where the power partition is really enabled. While at it, make sure that the runtime power management also works in ganged mode, which is currently also broken. Reported-by: Jonathan Hunter <jonathanh@nvidia.com> Tested-by: Jonathan Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* gpu: host1x: mipi: Power down regulators when unusedThierry Reding2015-08-131-12/+98
| | | | | | | Keep track of the number of users of DSI and CSI pads and power down the regulators that supply the bricks when all users are gone. Signed-off-by: Thierry Reding <treding@nvidia.com>
* gpu: host1x: mipi: Add Tegra210 supportThierry Reding2015-08-131-1/+35
| | | | | | | Some changes are needed to the configuration settings for some lanes. In addition, the clock lanes for the CSI pads can no longer be calibrated. Signed-off-by: Thierry Reding <treding@nvidia.com>
* gpu: host1x: mipi: Add Tegra132 supportThierry Reding2015-08-131-0/+18
| | | | | | | While Tegra132 has the same pads as Tegra124, some configuration values need to be programmed slightly differently. Signed-off-by: Thierry Reding <treding@nvidia.com>
* gpu: host1x: mipi: Constify OF match tableThierry Reding2015-08-131-1/+1
| | | | | | | This table is never modified and can therefore reside in read-only memory. Signed-off-by: Thierry Reding <treding@nvidia.com>
* gpu: host1x: mipi: Clear calibration statusThierry Reding2015-08-131-0/+4
| | | | | | | Before starting a new calibration cycle, make sure to clear the current status by writing a 1 to the various "calibration done" bits. Signed-off-by: Thierry Reding <treding@nvidia.com>
* gpu: host1x: mipi: Fix clock lane register for DSIThierry Reding2015-08-131-5/+5
| | | | | | | | Use more consistent names for the clock lane configuration registers and fix the offset of the upper clock lane configuration register for the first DSI pad. Signed-off-by: Thierry Reding <treding@nvidia.com>
* gpu: host1x: mipi: Parameterize to support future SoCsThierry Reding2015-08-131-8/+79
| | | | | | | Parameterize more of the register programming to accomodate for changes required by future SoC generations. Signed-off-by: Thierry Reding <treding@nvidia.com>
* gpu: host1x: mipi: Set MIPI_CAL_BIAS_PAD_CFG1 registerSean Paul2014-11-131-0/+4
| | | | | | | | During calibration, sets the "internal reference level for drive pull- down" to the value specified in the Tegra TRM. Signed-off-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
* gpu: host1x: mipi: Calibrate clock lanesSean Paul2014-11-131-32/+92
| | | | | | | | | Include the clock lanes when calibrating the MIPI PHY on Tegra124 compatible devices. Signed-off-by: Sean Paul <seanpaul@chromium.org> [treding@nvidia.com: bikeshedding] Signed-off-by: Thierry Reding <treding@nvidia.com>
* gpu: host1x: mipi: Preserve the contents of MIPI_CAL_CTRLSean Paul2014-11-131-1/+3
| | | | | | | | | | | | | | By paving the CTRL reg value, the current code changes MIPI_CAL_PRESCALE ("Auto-cal calibration step prescale") from 1us to 0.1us (val=0). In the description for PHY's noise filter (MIPI_CAL_NOISE_FLT), the TRM states that if the value of the prescale is 0 (or 0.1us), the filter should be set between 2-5. However, the current code sets it to 0. For now, let's keep the prescale and filter values as-is, which is most likely the power-on-reset values of 0x2 and 0xa, respectively. Signed-off-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
* gpu: host1x: mipi: Registers are 32 bits wideThierry Reding2014-11-131-8/+8
| | | | | | | | On 64-bit platforms an unsigned long would be 64 bit and cause unnecessary casting when being passed to writel() or returned from readl(). Make register values 32 bits wide to avoid that. Signed-off-by: Thierry Reding <treding@nvidia.com>
* gpu: host1x: Fix more sparse warningsThierry Reding2013-12-191-0/+3
| | | | | | | | Include the linux/host1x.h and dev.h headers so that function prototypes are visible to keep sparse from suggesting that their implementations be made static. Signed-off-by: Thierry Reding <treding@nvidia.com>
* gpu: host1x: Add MIPI pad calibration supportThierry Reding2013-12-191-0/+272
This driver adds support to perform calibration of the MIPI pads for CSI and DSI. Signed-off-by: Thierry Reding <treding@nvidia.com>
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