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* drm/i915: Remove spurious semicolonsDamien Lespiau2014-04-095-5/+5
| | | | | | | | | | Found by running the semicolon.cocci spatch: https://github.com/coccinelle/coccinellery/blob/master/semicolon/semicolon.cocci Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915/chv: Add IS_CHERRYVIEW() macroVille Syrjälä2014-04-091-0/+1
| | | | | | | | We will treat Cherryview like Valleyview for most parts. Add a macro for cases when we need to tell the two apart. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915/chv: IS_BROADWELL() should not be true for CherryviewVille Syrjälä2014-04-091-1/+1
| | | | | | Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915: Enable RANDOM resolution support for MIPI panelsShobhit Kumar2014-04-091-1/+6
| | | | | | | | | Some MIPI panels might not have resolution which is a multiple of 64 like 1366x768. Enable this feature for such panels by default Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915: Send DPI command explicitely in LP modeShobhit Kumar2014-04-093-5/+9
| | | | | | | | | | Though HS mode also should work. v2: Change parameter as "bool hs" as suggested by Jani Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915: Panel commands can be sent only when clock is in LP11Shobhit Kumar2014-04-091-0/+17
| | | | | | Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915: Parameterize the Clockstop and escape_clk_divShobhit Kumar2014-04-092-3/+12
| | | | | | | | In preparation for Generic driver Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915: Disable DPOunit clock gatingShobhit Kumar2014-04-091-2/+24
| | | | | | | | | Otherwise, this can stall pipe. We also need DPLL REFA always enabled Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915: Enable MIPI port before the plane and pipe enableShobhit Kumar2014-04-091-18/+33
| | | | | | | | | | As per the hw team's recommendation we need to enable the MIPI port before enabling the plane and pipe. So call MIPI port enable in pre_enable phase itself Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915: Program Rcomp and band gap reset everytime we resume from power gateShobhit Kumar2014-04-091-3/+9
| | | | | | Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915: Add more registers to the whitelist for mesaBrad Volkin2014-04-092-0/+19
| | | | | | | | | | | | These are additional registers needed for performance monitoring and ARB_draw_indirect extensions in mesa. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=76719 Cc: Kenneth Graunke <kenneth@whitecape.org> Signed-off-by: Brad Volkin <bradley.d.volkin@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> [danvet: Squash in fixup from Brad requested by Ken.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915: Remove misleading debug messageDamien Lespiau2014-04-091-3/+0
| | | | | | | | | | haswell_write_eld() is also used on broadwell, so let's not explicitely mention Haswell. The rest of the function has plenty of debug output which will print the function name, so we know where we are anyway. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915: Rename GEN8_PIPE_FLIP_DONE to PRIMARY_FLIP_DONEDamien Lespiau2014-04-092-3/+3
| | | | | | | | | It is now clear that this interrupt is for the primary plane and not something global to the pipe. It also matches what the spec calls it. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915: add flags to i915_ring_stopMika Kuoppala2014-04-093-6/+27
| | | | | | | | | | | | | | | | | | | Piglit runner and QA are both looking at the dmesg for DRM_ERRORs with test cases. Add a flag to control those when we they are expected from related test cases. Also add flag to control if contexts should be banned that introduced the hang. Hangcheck is timer based and preventing bans by adding sleeps to testcases makes testing slower. v2: intel_ring_stopped(), readable comment (Chris) v3: keep compatibility (Daniel) References: https://bugs.freedesktop.org/show_bug.cgi?id=75876 Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915: dma_buf_vunmap is presumed not to fail, don't let itChris Wilson2014-04-091-5/+1
| | | | | | | | | | | | | | | Since dma_buf_vunmap() procedes blithely on ignorant of whether the driver failed to actually unmap the backing storage for the dma-buf, we need to make a best-effort to do so. This involves not allowing ourselves to be susceptible to signals causing us to leak the storage. This should have been detectable with the current i-g-t as a misplaced signal should have left the pages pinned upon freeing the object where we have a warning in place. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915/bdw: Use the GEN8 SRM when qeueing a flipDamien Lespiau2014-04-091-3/+19
| | | | | | | | | Comment from Ben: It's a bit unclear whether we need this dance still on bdw. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Reviewed-by: Ben Widawsky <ben@bwidawsk.net> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915/bdw: Provide a gen8 version of SRMDamien Lespiau2014-04-091-0/+1
| | | | | | | | GEN8 now has a qword to code for 48bit addresses. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Reviewed-by: Ben Widawsky <ben@bwidawsk.net> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915: Protect the argument expansion in LRI and SRM macrosDamien Lespiau2014-04-091-2/+2
| | | | | | | | | It seems like it wouldn't be too unlikely to be wanting to use a an expression in the macro argument and things could go very wrong. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Reviewed-by: Ben Widawsky <ben@bwidawsk.net> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915: move infoframe setting to after pll enable v3Jesse Barnes2014-04-091-2/+16
| | | | | | | | | | | | Needs to happen after clock is running or it doesn't behave correctly. v2: fix subject (Ville) make it clearer that this occurs in pre_enable (Paulo) misc bikesheds (Paulo) Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915: enable HDMI mode on VLV when an HDMI sink is detectedJesse Barnes2014-04-091-2/+2
| | | | | | | | Allows sending of the null packets for conformance. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915/vlv: disable AVI infoframe emission when writing infoframesJesse Barnes2014-04-091-2/+2
| | | | | | | | | We also do a disable later when we write a specific infoframe, but here we do it to prevent sending a stale one before updating the infoframes. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915/vlv: write the port field in the per-pipe DIP control regJesse Barnes2014-04-091-0/+12
| | | | | | | | In case we end up bouncing these around between ports. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i916: Refactor WM register maximumsVille Syrjälä2014-04-091-29/+37
| | | | | | | | | We will have another use for the maximum watermark values that the registers can hold. Pull those out into separate functions. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915: Skip watermark merging for inactive pipesVille Syrjälä2014-04-091-2/+5
| | | | | | | | | | Even though the inactive pipes should have their watermarks set to all 0 with enable=true, we can possibly shave off a few cycles by completely skipping the merge procedure for inactive pipes. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915: Add some more tracked state to intel_pipe_wmVille Syrjälä2014-04-092-21/+46
| | | | | | | | | | | | | | | | intel_pipe_wm will be used to track the state in different stages of the watermark update process. For that we need to keep a bit more state in intel_pipe_wm. We also need to separate the multi-pipe intel_wm_config computation from ilk_compute_wm_parameters() as that one deals with the future state, and we need the intel_wm_config to match the current hardware state at the time we do the watermark merging for multiple pipes. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> [danvet: Frob conflict.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915: Dump the whole context object.Ben Widawsky2014-04-091-14/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | As we've learned over time, the HW context is just a series of GPU commands that we're able to decode without any changes in intel_error_decode. Since many bugs recently have been implicated in the HW context state, it makes sense to dump the whole context object in a form which can be parsed. Sample: render ring --- HW Context = 0x042db000 ringbuffer (render ring) at 0x0160c000; HEAD points to: 0x0160c000 0x0160c000: 0x00000000: MI_NOOP 0x0160c004: 0x00000000: MI_NOOP 0x0160c008: 0x00000000: MI_NOOP 0x0160c00c: 0x00000000: MI_NOOP 0x0160c010: 0x00000000: MI_NOOP 0x0160c014: 0x00000000: MI_NOOP 0x0160c018: 0x00000000: MI_NOOP 0x0160c01c: 0x00000000: MI_NOOP Unfortunately, our decoder isn't quite smart enough to deal with the variable length LRIs - but that is a tools problem. Signed-off-by: Ben Widawsky <ben@bwidawsk.net> [danvet: Clarify commit message a bit, seems to have lost a few crucial words.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915: warn when a vblank wait times outJesse Barnes2014-04-091-1/+1
| | | | | | | This always indicates a bug somewhere. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915: Unref context on failed eb_createBen Widawsky2014-04-091-1/+2
| | | | | | | | | | | | | | | | | I opted to do this instead of grabbing the context reference after eb_create since eb_create can potentially call the shrinker, and that makes things very complicated. This simple patch balances the ref count without requiring a great deal of review to make sure the shrinker path is safe. Theoretically (by design) the shrinker can end up destroying a context, which enforces the reasoning for doing the fix this way instead of moving the reference to later in the function. Cc: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Ben Widawsky <ben@bwidawsk.net> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915: Don't read sprite LP2+ registers on ILK/SNBVille Syrjälä2014-04-091-2/+4
| | | | | | | | Sprite LP2+ registers don't exist on ILK/SNB so don't read them. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915: Make contexts non-snooped on non-LLC platformsVille Syrjälä2014-04-091-1/+9
| | | | | | | | | | | | | We don't do CPU access to GPU contexts so making the GPU access snoop the CPU caches seems silly, and potentially expensive. v2: Use !IS_VALLEYVIEW instead of HAS_LLC as this is really about what the PTEs can represent. Add a comment clarifying the situation. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915/vlv:Implement the WA 'WaDisable_RenderCache_OperationalFlush'Akash Goel2014-04-092-0/+25
| | | | | | | | | | | | | | | | | | | | | On Gen4+ platforms (except BDW), Render Cache Operational flush cannot be enabled. This WA is apparently required for all Gen4+ platforms,except BDW. In BDW, the bit has been repurposed otherwise. This has been tested only on vlv. v2: Corrected the code regarding the wrong usage of MASKED_BIT_DISABLE (Chris) v3: Enhancing the scope of WA to Gen4+ platforms except BDW (Ville) v4: Adding WA for g4x, crestline, broadwater (Ville) Signed-off-by: Akash Goel <akash.goel@intel.com> Signed-off-by: Sourab Gupta <sourab.gupta@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* Merge remote-tracking branch 'airlied/drm-next' into HEADDaniel Vetter2014-04-09339-8868/+24353
|\ | | | | | | | | | | | | | | Backmerge drm-next after the big s/crtc->fb/crtc->primary->fb/ cocinelle patch to avoid endless amounts of conflict hilarity in my -next queue for 3.16. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| * DRM: armada: fix corruption while loading cursorsRussell King2014-04-081-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Loading cursors to the LCD controller's SRAM can be corrupted when the configured pixel clock is relatively slow. This seems to be caused when we write back-to-back to the SRAM registers. There doesn't appear to be any status register we can read to check when an access has completed. Inserting a dummy read between the writes appears to fix the problem. Cc: <stable@vger.kernel.org> # 3.13 Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Dave Airlie <airlied@redhat.com>
| * Merge tag 'drm-intel-fixes-2014-04-04' of ↵Dave Airlie2014-04-0528-412/+608
| |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://anongit.freedesktop.org/drm-intel into drm-next Merge window -fixes pull request as usual. Well, I did sneak in Jani's drm_i915_private_t typedef removal, need to have fun with a big sed job too ;-) Otherwise: - hdmi interlaced fixes (Jesse&Ville) - pipe error/underrun/crc tracking fixes, regression in late 3.14-rc (but not cc: stable since only really relevant for igt runs) - large cursor wm fixes (Chris) - fix gpu turbo boost/throttle again, was getting stuck due to vlv rps patches (Chris+Imre) - fix runtime pm fallout (Paulo) - bios framebuffer inherit fix (Chris) - a few smaller things * tag 'drm-intel-fixes-2014-04-04' of git://anongit.freedesktop.org/drm-intel: (196 commits) Skip intel_crt_init for Dell XPS 8700 drm/i915: vlv: fix RPS interrupt mask setting Revert "drm/i915/vlv: fixup DDR freq detection per Punit spec" drm/i915: move power domain init earlier during system resume drm/i915: Fix the computation of required fb size for pipe drm/i915: don't get/put runtime PM at the debugfs forcewake file drm/i915: fix WARNs when reading DDI state while suspended drm/i915: don't read cursor registers on powered down pipes drm/i915: get runtime PM at i915_display_info drm/i915: don't read pp_ctrl_reg if we're suspended drm/i915: get runtime PM at i915_reg_read_ioctl drm/i915: don't schedule force_wake_timer at gen6_read drm/i915: vlv: reserve the GT power context only once during driver init drm/i915: prefer struct drm_i915_private to drm_i915_private_t drm/i915/overlay: prefer struct drm_i915_private to drm_i915_private_t drm/i915/ringbuffer: prefer struct drm_i915_private to drm_i915_private_t drm/i915/display: prefer struct drm_i915_private to drm_i915_private_t drm/i915/irq: prefer struct drm_i915_private to drm_i915_private_t drm/i915/gem: prefer struct drm_i915_private to drm_i915_private_t drm/i915/dma: prefer struct drm_i915_private to drm_i915_private_t ...
| | * Skip intel_crt_init for Dell XPS 8700Giacomo Comes2014-04-041-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Dell XPS 8700 has a onboard Display port and HDMI port and no VGA port. The call intel_crt_init freeze the machine, so skip such call. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=73559 Signed-off-by: Giacomo Comes <comes at naic.edu> Cc: stable@vger.kernel.org Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| | * drm/i915: vlv: fix RPS interrupt mask settingImre Deak2014-04-041-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This typo may lead to missed RPS interrupts and as a result a too low or too high frequency for the current workload. The interrupt mask will be set properly at a subsequent GPU idle event, but can get corrupted again at the next RPS up/down event. Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| | * Revert "drm/i915/vlv: fixup DDR freq detection per Punit spec"Deepak S2014-04-041-4/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As per the inputs provided by hardware team we still use DDR Rates as 0,1=800, 2=1066, 3=1333. With this change, Turbo freqs used on current machines matches. This reverts commit f64a28a7c5ab2fc342326de9e126acf3cc0f91d6. commit f64a28a7c5ab2fc342326de9e126acf3cc0f91d6 Author: Jesse Barnes <jbarnes@virtuousgeek.org> Date: Mon Nov 4 16:07:00 2013 -0800 drm/i915/vlv: fixup DDR freq detection per Punit spec v2: Add reference to previous commit which changed this. (Daniel) Acked-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Deepak S <deepak.s@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| | * drm/i915: move power domain init earlier during system resumeImre Deak2014-04-041-14/+76
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | During resume the intel hda audio driver depends on the i915 driver reinitializing the audio power domain. Since the order of calling the i915 resume handler wrt. that of the audio driver is not guaranteed, move the power domain reinitialization step to the resume_early handler. This is guaranteed to run before the resume handler of any other driver. The power domain initialization in turn requires us to enable the i915 pci device first, so move that part earlier too. Accordingly disabling of the i915 pci device should happen after the audio suspend handler ran. So move the disabling later from the i915 resume handler to the resume_late handler. v2: - move intel_uncore_sanitize/early_sanitize earlier too, so they don't get reordered wrt. intel_power_domains_init_hw() Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=76152 Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Takashi Iwai <tiwai@suse.de> Cc: stable@vger.kernel.org [danvet: Add cc: stable and loud comments that this is just a hack.] [danvet: Fix "Should it be static?" sparse warning reported by Wu Fengguang's kbuilder.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| | * drm/i915: Fix the computation of required fb size for pipeChris Wilson2014-04-021-8/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The computation of required framebuffer size in commit d978ef14456a38034f6c0e94a794129501f89200 Author: Jesse Barnes <jbarnes@virtuousgeek.org> Date: Fri Mar 7 08:57:51 2014 -0800 drm/i915: Wrap the preallocated BIOS framebuffer and preserve for KMS fbcon v12 is too optimistic, and would rely on the invariant fb being reconstructed to exactly fit each pipe (and probably ignore hardware limits). Instead, we want to compute the upper bound on what the display engine will access and ensure that is within the inherited framebuffer. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| * | Merge tag 'drm/tegra/for-3.15-rc1' of ↵Dave Airlie2014-04-0517-100/+2071
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://anongit.freedesktop.org/tegra/linux into drm-next drm/tegra: Changes for v3.15-rc1 Implement eDP support for Tegra124 and support the PRIME vmap()/vunmap() operations. A symbol that is required for upcoming V4L2 support is now exported by the host1x driver. Relicense drivers under the GPL v2 for consistency. One exception is the public header file, which is relicensed under MIT to abide by the common rule. * tag 'drm/tegra/for-3.15-rc1' of git://anongit.freedesktop.org/tegra/linux: drm/tegra: Use standard GPL v2 license text drm/tegra: Relicense under GPL v2 drm/tegra: Relicense public header under MIT drm/tegra: Add eDP support gpu: host1x: export host1x_syncpt_incr_max() function drm/tegra: prime: Add vmap support
| | * | drm/tegra: Use standard GPL v2 license textThierry Reding2014-04-041-11/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Use the more canonical and concise variant of the GPL v2 license text. Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| | * | drm/tegra: Relicense under GPL v2Thierry Reding2014-04-046-87/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The majority of the code in this driver is licensed under the GPL v2, so relicense the rest under GPL v2 as well for consistency. Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| | * | drm/tegra: Add eDP supportThierry Reding2014-04-049-2/+2035
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for eDP functionality found on Tegra124 and later SoCs. Only fast link training is currently supported. Signed-off-by: Thierry Reding <treding@nvidia.com>
| | * | gpu: host1x: export host1x_syncpt_incr_max() functionBryan Wu2014-04-041-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Tegra V4L2 camera driver needs this function to do frame capture. Signed-off-by: Bryan Wu <pengw@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| | * | drm/tegra: prime: Add vmap supportThierry Reding2014-04-041-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This is trivial to support since all GEM objects are mapped into kernel space anyway. Signed-off-by: Thierry Reding <treding@nvidia.com>
| * | | Merge tag 'drm/panel/for-3.15-rc1' of ↵Dave Airlie2014-04-051-51/+106
| |\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://anongit.freedesktop.org/tegra/linux into drm-next drm/panel: Changes for v3.15-rc1 Add support for a couple more simple panels. A few cleanups to the simple panel driver are also included (gpiod interface conversion, removal of redundant call to regulator_disable()). * tag 'drm/panel/for-3.15-rc1' of git://anongit.freedesktop.org/tegra/linux: drm/panel: add support for LG LD070WX3-SL01 panel drm/panel: add support for LG LH500WX1-SD03 panel drm/panel: simple: Allow DSI panels to provide mode flags drm/panel: simple: Allow GPIO accesses to sleep drm/panel: remove redundant regulator_disable() drm/panel: use gpiod interface for enable GPIO drm/panel: Add LG 12.9" LCD panel MAINTAINERS: Add entry for DRM panel drivers Conflicts: MAINTAINERS
| | * | | drm/panel: add support for LG LD070WX3-SL01 panelAlexandre Courbot2014-04-041-0/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This panel is used by Tegra Note 7 and supported by the simple-panel driver. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| | * | | drm/panel: add support for LG LH500WX1-SD03 panelAlexandre Courbot2014-04-041-0/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This panel is used by the NVIDIA SHIELD and supported by the simple-panel driver. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| | * | | drm/panel: simple: Allow DSI panels to provide mode flagsThierry Reding2014-04-041-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In order to differentiate between the different video modes (burst vs. non-burst, sync pulses vs. sync events) supported by peripherals, pass the flags that specify this mode in the panel description to the DSI peripheral device when probed. Signed-off-by: Thierry Reding <treding@nvidia.com>
| | * | | drm/panel: simple: Allow GPIO accesses to sleepThierry Reding2014-04-041-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The enable GPIO for panels may be provided by GPIO expanders on slow busses (such as I2C), and therefore toggling the GPIO may sleep. Since these accesses don't happen in interrupt context, use the *_cansleep() variants of the GPIO API. Signed-off-by: Thierry Reding <treding@nvidia.com>
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