From 94aed538e032d82287023beb9c59ee80f03a1493 Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Tue, 24 May 2016 13:41:02 -0400 Subject: ARM: dts: exynos: Add async-bridge clock to MFC power domain for Exynos5420 The MFC IP is also inter-connected by an Async-Bridge so the CLK_ACLK333 has to be ungated during a power domain switch. Trying to do it when the clock is gated will fail and lead to an imprecise external abort error when the driver tries to access the MFC registers with the PD disabled. For example, if the s5p-mfc module is removed and the MFC PD turned off: [ 186.835606] Power domain power-domain@10044060 disable failed [ 186.835671] s5p-mfc 11000000.codec: Removing 11000000.codec [ 186.837670] Power domain power-domain@10044060 disable failed And when the module is inserted again: [ 2395.176956] s5p_mfc_wait_for_done_dev:34: Interrupt (dev->int_type:0, command:12) timed out [ 2395.177031] s5p_mfc_init_hw:272: Failed to load firmware [ 2395.177384] Unhandled fault: imprecise external abort (0x1406) at 0x00000000 [ 2395.177441] pgd = ec3b4000 [ 2395.177467] [00000000] *pgd=00000000 [ 2395.177507] Internal error: : 1406 [#1] PREEMPT SMP ARM [ 2395.177550] Modules linked in: s5p_mfc mwifiex_sdio mwifiex uvcvideo s5p_jpeg v4l2_mem2mem videobuf2_vmalloc videobuf2_dma_contig videobuf2_memops videobuf2_v4l2 videobuf2_core v4l2_common videodev media [last unloaded: s5p_mfc] [ 2395.177774] CPU: 1 PID: 2382 Comm: v4l_id Tainted: G W 4.6.0-rc6-next-20160502-00010-g7730dc64d2c1-dirty #179 [ 2395.177857] Hardware name: SAMSUNG EXYNOS (Flattened Device Tree) [ 2395.177906] task: ed275500 ti: e6c8c000 task.ti: e6c8c000 [ 2395.177996] PC is at s5p_mfc_reset+0x1c4/0x284 [s5p_mfc] [ 2395.178057] LR is at s5p_mfc_reset+0x1a4/0x284 [s5p_mfc] This patch fixes this issue by adding the CLK_ACLK333 as an Async-Bridge clock for the MFC power domain, so the PD configuration works properly. Signed-off-by: Javier Martinez Canillas Reviewed-by: Krzysztof Kozlowski Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos5420.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'arch/arm/boot/dts/exynos5420.dtsi') diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index c6e05eb88937..b4d43e3c18a0 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -349,8 +349,9 @@ mfc_pd: power-domain@10044060 { compatible = "samsung,exynos4210-pd"; reg = <0x10044060 0x20>; - clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MOUT_USER_ACLK333>; - clock-names = "oscclk", "clk0"; + clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MOUT_USER_ACLK333>, + <&clock CLK_ACLK333>; + clock-names = "oscclk", "clk0","asb0"; #power-domain-cells = <0>; }; -- cgit v1.2.1 From 7b336fc88b9e2c981aeb3da33b2d7b4bc1f910f0 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 10 May 2016 20:16:57 +0200 Subject: ARM: dts: exynos: Replace deprecated hsi2c compatible on Exynos5420 Since commit 218e1496135e ("i2c: exynos5: add support for HSI2C on Exynos5260 SoC") the "samsung,exynos5-hsi2c" is deprecated in favor of SoC version specific: "samsung,exynos5250-hsi2c". Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos5420.dtsi | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) (limited to 'arch/arm/boot/dts/exynos5420.dtsi') diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index c6e05eb88937..9d99e43afe58 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -681,7 +681,7 @@ }; hsi2c_4: i2c@12CA0000 { - compatible = "samsung,exynos5-hsi2c"; + compatible = "samsung,exynos5250-hsi2c"; reg = <0x12CA0000 0x1000>; interrupts = <0 60 0>; #address-cells = <1>; @@ -694,7 +694,7 @@ }; hsi2c_5: i2c@12CB0000 { - compatible = "samsung,exynos5-hsi2c"; + compatible = "samsung,exynos5250-hsi2c"; reg = <0x12CB0000 0x1000>; interrupts = <0 61 0>; #address-cells = <1>; @@ -707,7 +707,7 @@ }; hsi2c_6: i2c@12CC0000 { - compatible = "samsung,exynos5-hsi2c"; + compatible = "samsung,exynos5250-hsi2c"; reg = <0x12CC0000 0x1000>; interrupts = <0 62 0>; #address-cells = <1>; @@ -720,7 +720,7 @@ }; hsi2c_7: i2c@12CD0000 { - compatible = "samsung,exynos5-hsi2c"; + compatible = "samsung,exynos5250-hsi2c"; reg = <0x12CD0000 0x1000>; interrupts = <0 63 0>; #address-cells = <1>; @@ -733,7 +733,7 @@ }; hsi2c_8: i2c@12E00000 { - compatible = "samsung,exynos5-hsi2c"; + compatible = "samsung,exynos5250-hsi2c"; reg = <0x12E00000 0x1000>; interrupts = <0 87 0>; #address-cells = <1>; @@ -746,7 +746,7 @@ }; hsi2c_9: i2c@12E10000 { - compatible = "samsung,exynos5-hsi2c"; + compatible = "samsung,exynos5250-hsi2c"; reg = <0x12E10000 0x1000>; interrupts = <0 88 0>; #address-cells = <1>; @@ -759,7 +759,7 @@ }; hsi2c_10: i2c@12E20000 { - compatible = "samsung,exynos5-hsi2c"; + compatible = "samsung,exynos5250-hsi2c"; reg = <0x12E20000 0x1000>; interrupts = <0 203 0>; #address-cells = <1>; -- cgit v1.2.1 From 5a124fe0b1d7e921d250c0352b48148e280ad9f4 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 3 May 2016 14:51:25 +0200 Subject: ARM: dts: exynos: Move common nodes to exynos5.dtsi Exynos5420 and Exynos5250 share some nodes: the PWM, syscon (sysreg_system_controller) and first four I2C controllers. Move them to parent DTSI to avoid duplication. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Javier Martinez Canillas Tested-by: Javier Martinez Canillas --- arch/arm/boot/dts/exynos5420.dtsi | 108 ++++++++++++-------------------------- 1 file changed, 34 insertions(+), 74 deletions(-) (limited to 'arch/arm/boot/dts/exynos5420.dtsi') diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index 9d99e43afe58..5bf7882e44a1 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -30,10 +30,6 @@ pinctrl2 = &pinctrl_2; pinctrl3 = &pinctrl_3; pinctrl4 = &pinctrl_4; - i2c0 = &i2c_0; - i2c1 = &i2c_1; - i2c2 = &i2c_2; - i2c3 = &i2c_3; i2c4 = &hsi2c_4; i2c5 = &hsi2c_5; i2c6 = &hsi2c_6; @@ -578,15 +574,6 @@ status = "disabled"; }; - pwm: pwm@12dd0000 { - compatible = "samsung,exynos4210-pwm"; - reg = <0x12dd0000 0x100>; - samsung,pwm-outputs = <0>, <1>, <2>, <3>; - #pwm-cells = <3>; - clocks = <&clock CLK_PWM>; - clock-names = "timers"; - }; - dp_phy: dp-video-phy { compatible = "samsung,exynos5420-dp-video-phy"; samsung,pmu-syscon = <&pmu_system_controller>; @@ -624,62 +611,7 @@ status = "disabled"; }; - i2c_0: i2c@12C60000 { - compatible = "samsung,s3c2440-i2c"; - reg = <0x12C60000 0x100>; - interrupts = <0 56 0>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clock CLK_I2C0>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_bus>; - samsung,sysreg-phandle = <&sysreg_system_controller>; - status = "disabled"; - }; - - i2c_1: i2c@12C70000 { - compatible = "samsung,s3c2440-i2c"; - reg = <0x12C70000 0x100>; - interrupts = <0 57 0>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clock CLK_I2C1>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_bus>; - samsung,sysreg-phandle = <&sysreg_system_controller>; - status = "disabled"; - }; - - i2c_2: i2c@12C80000 { - compatible = "samsung,s3c2440-i2c"; - reg = <0x12C80000 0x100>; - interrupts = <0 58 0>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clock CLK_I2C2>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_bus>; - samsung,sysreg-phandle = <&sysreg_system_controller>; - status = "disabled"; - }; - - i2c_3: i2c@12C90000 { - compatible = "samsung,s3c2440-i2c"; - reg = <0x12C90000 0x100>; - interrupts = <0 59 0>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clock CLK_I2C3>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_bus>; - samsung,sysreg-phandle = <&sysreg_system_controller>; - status = "disabled"; - }; - + /* i2c_0-3 are defined in exynos5.dtsi */ hsi2c_4: i2c@12CA0000 { compatible = "samsung,exynos5250-hsi2c"; reg = <0x12CA0000 0x1000>; @@ -859,11 +791,6 @@ interrupt-parent = <&gic>; }; - sysreg_system_controller: syscon@10050000 { - compatible = "samsung,exynos5-sysreg", "syscon"; - reg = <0x10050000 0x5000>; - }; - tmu_cpu0: tmu@10060000 { compatible = "samsung,exynos5420-tmu"; reg = <0x10060000 0x100>; @@ -1614,6 +1541,39 @@ iommu-names = "m0", "m1"; }; +&i2c_0 { + clocks = <&clock CLK_I2C0>; + clock-names = "i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_bus>; +}; + +&i2c_1 { + clocks = <&clock CLK_I2C1>; + clock-names = "i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_bus>; +}; + +&i2c_2 { + clocks = <&clock CLK_I2C2>; + clock-names = "i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_bus>; +}; + +&i2c_3 { + clocks = <&clock CLK_I2C3>; + clock-names = "i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_bus>; +}; + +&pwm { + clocks = <&clock CLK_PWM>; + clock-names = "timers"; +}; + &rtc { clocks = <&clock CLK_RTC>; clock-names = "rtc"; -- cgit v1.2.1 From 5d99cc59a3c63489c1b3fbab34a69c01dad4788e Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 3 May 2016 18:53:04 +0200 Subject: ARM: dts: exynos: Move Exynos5250 and Exynos5420 nodes under soc The conventions is to put SoC devices under 'soc' node. In fact other our DTSes (like exynos3250.dtsi or exynos5410.dtsi) already follow it. Adjust exynos5250 and exynos5420 DTSI to follow this convention. This is also necessary for the upcoming change in exynos5410.dtsi to inherit from common exynos5.dtsi. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Javier Martinez Canillas Tested-by: Javier Martinez Canillas --- arch/arm/boot/dts/exynos5420.dtsi | 2763 +++++++++++++++++++------------------ 1 file changed, 1383 insertions(+), 1380 deletions(-) (limited to 'arch/arm/boot/dts/exynos5420.dtsi') diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index 5bf7882e44a1..b65bdbe2e563 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -46,1480 +46,1483 @@ usbdrdphy1 = &usbdrd_phy1; }; - cluster_a15_opp_table: opp_table0 { - compatible = "operating-points-v2"; - opp-shared; - opp@1800000000 { - opp-hz = /bits/ 64 <1800000000>; - opp-microvolt = <1250000>; - clock-latency-ns = <140000>; - }; - opp@1700000000 { - opp-hz = /bits/ 64 <1700000000>; - opp-microvolt = <1212500>; - clock-latency-ns = <140000>; - }; - opp@1600000000 { - opp-hz = /bits/ 64 <1600000000>; - opp-microvolt = <1175000>; - clock-latency-ns = <140000>; - }; - opp@1500000000 { - opp-hz = /bits/ 64 <1500000000>; - opp-microvolt = <1137500>; - clock-latency-ns = <140000>; - }; - opp@1400000000 { - opp-hz = /bits/ 64 <1400000000>; - opp-microvolt = <1112500>; - clock-latency-ns = <140000>; - }; - opp@1300000000 { - opp-hz = /bits/ 64 <1300000000>; - opp-microvolt = <1062500>; - clock-latency-ns = <140000>; - }; - opp@1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <1037500>; - clock-latency-ns = <140000>; - }; - opp@1100000000 { - opp-hz = /bits/ 64 <1100000000>; - opp-microvolt = <1012500>; - clock-latency-ns = <140000>; - }; - opp@1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = < 987500>; - clock-latency-ns = <140000>; - }; - opp@900000000 { - opp-hz = /bits/ 64 <900000000>; - opp-microvolt = < 962500>; - clock-latency-ns = <140000>; - }; - opp@800000000 { - opp-hz = /bits/ 64 <800000000>; - opp-microvolt = < 937500>; - clock-latency-ns = <140000>; - }; - opp@700000000 { - opp-hz = /bits/ 64 <700000000>; - opp-microvolt = < 912500>; - clock-latency-ns = <140000>; - }; - }; - - cluster_a7_opp_table: opp_table1 { - compatible = "operating-points-v2"; - opp-shared; - opp@1300000000 { - opp-hz = /bits/ 64 <1300000000>; - opp-microvolt = <1275000>; - clock-latency-ns = <140000>; - }; - opp@1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <1212500>; - clock-latency-ns = <140000>; - }; - opp@1100000000 { - opp-hz = /bits/ 64 <1100000000>; - opp-microvolt = <1162500>; - clock-latency-ns = <140000>; - }; - opp@1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <1112500>; - clock-latency-ns = <140000>; - }; - opp@900000000 { - opp-hz = /bits/ 64 <900000000>; - opp-microvolt = <1062500>; - clock-latency-ns = <140000>; - }; - opp@800000000 { - opp-hz = /bits/ 64 <800000000>; - opp-microvolt = <1025000>; - clock-latency-ns = <140000>; - }; - opp@700000000 { - opp-hz = /bits/ 64 <700000000>; - opp-microvolt = <975000>; - clock-latency-ns = <140000>; - }; - opp@600000000 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <937500>; - clock-latency-ns = <140000>; - }; - }; - /* * The 'cpus' node is not present here but instead it is provided * by exynos5420-cpus.dtsi or exynos5422-cpus.dtsi. */ - cci: cci@10d20000 { - compatible = "arm,cci-400"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x10d20000 0x1000>; - ranges = <0x0 0x10d20000 0x6000>; - - cci_control0: slave-if@4000 { - compatible = "arm,cci-400-ctrl-if"; - interface-type = "ace"; - reg = <0x4000 0x1000>; - }; - cci_control1: slave-if@5000 { - compatible = "arm,cci-400-ctrl-if"; - interface-type = "ace"; - reg = <0x5000 0x1000>; + soc: soc { + cluster_a15_opp_table: opp_table0 { + compatible = "operating-points-v2"; + opp-shared; + opp@1800000000 { + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <1250000>; + clock-latency-ns = <140000>; + }; + opp@1700000000 { + opp-hz = /bits/ 64 <1700000000>; + opp-microvolt = <1212500>; + clock-latency-ns = <140000>; + }; + opp@1600000000 { + opp-hz = /bits/ 64 <1600000000>; + opp-microvolt = <1175000>; + clock-latency-ns = <140000>; + }; + opp@1500000000 { + opp-hz = /bits/ 64 <1500000000>; + opp-microvolt = <1137500>; + clock-latency-ns = <140000>; + }; + opp@1400000000 { + opp-hz = /bits/ 64 <1400000000>; + opp-microvolt = <1112500>; + clock-latency-ns = <140000>; + }; + opp@1300000000 { + opp-hz = /bits/ 64 <1300000000>; + opp-microvolt = <1062500>; + clock-latency-ns = <140000>; + }; + opp@1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1037500>; + clock-latency-ns = <140000>; + }; + opp@1100000000 { + opp-hz = /bits/ 64 <1100000000>; + opp-microvolt = <1012500>; + clock-latency-ns = <140000>; + }; + opp@1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = < 987500>; + clock-latency-ns = <140000>; + }; + opp@900000000 { + opp-hz = /bits/ 64 <900000000>; + opp-microvolt = < 962500>; + clock-latency-ns = <140000>; + }; + opp@800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = < 937500>; + clock-latency-ns = <140000>; + }; + opp@700000000 { + opp-hz = /bits/ 64 <700000000>; + opp-microvolt = < 912500>; + clock-latency-ns = <140000>; + }; + }; + + cluster_a7_opp_table: opp_table1 { + compatible = "operating-points-v2"; + opp-shared; + opp@1300000000 { + opp-hz = /bits/ 64 <1300000000>; + opp-microvolt = <1275000>; + clock-latency-ns = <140000>; + }; + opp@1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1212500>; + clock-latency-ns = <140000>; + }; + opp@1100000000 { + opp-hz = /bits/ 64 <1100000000>; + opp-microvolt = <1162500>; + clock-latency-ns = <140000>; + }; + opp@1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <1112500>; + clock-latency-ns = <140000>; + }; + opp@900000000 { + opp-hz = /bits/ 64 <900000000>; + opp-microvolt = <1062500>; + clock-latency-ns = <140000>; + }; + opp@800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <1025000>; + clock-latency-ns = <140000>; + }; + opp@700000000 { + opp-hz = /bits/ 64 <700000000>; + opp-microvolt = <975000>; + clock-latency-ns = <140000>; + }; + opp@600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <937500>; + clock-latency-ns = <140000>; + }; + }; + + cci: cci@10d20000 { + compatible = "arm,cci-400"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x10d20000 0x1000>; + ranges = <0x0 0x10d20000 0x6000>; + + cci_control0: slave-if@4000 { + compatible = "arm,cci-400-ctrl-if"; + interface-type = "ace"; + reg = <0x4000 0x1000>; + }; + cci_control1: slave-if@5000 { + compatible = "arm,cci-400-ctrl-if"; + interface-type = "ace"; + reg = <0x5000 0x1000>; + }; + }; + + sysram@02020000 { + compatible = "mmio-sram"; + reg = <0x02020000 0x54000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x02020000 0x54000>; + + smp-sysram@0 { + compatible = "samsung,exynos4210-sysram"; + reg = <0x0 0x1000>; + }; + + smp-sysram@53000 { + compatible = "samsung,exynos4210-sysram-ns"; + reg = <0x53000 0x1000>; + }; + }; + + clock: clock-controller@10010000 { + compatible = "samsung,exynos5420-clock"; + reg = <0x10010000 0x30000>; + #clock-cells = <1>; + }; + + clock_audss: audss-clock-controller@3810000 { + compatible = "samsung,exynos5420-audss-clock"; + reg = <0x03810000 0x0C>; + #clock-cells = <1>; + clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MAU_EPLL>, + <&clock CLK_SCLK_MAUDIO0>, <&clock CLK_SCLK_MAUPCM0>; + clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in"; + }; + + mfc: codec@11000000 { + compatible = "samsung,mfc-v7"; + reg = <0x11000000 0x10000>; + interrupts = <0 96 0>; + clocks = <&clock CLK_MFC>; + clock-names = "mfc"; + power-domains = <&mfc_pd>; + iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>; + iommu-names = "left", "right"; + }; + + mmc_0: mmc@12200000 { + compatible = "samsung,exynos5420-dw-mshc-smu"; + interrupts = <0 75 0>; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x12200000 0x2000>; + clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>; + clock-names = "biu", "ciu"; + fifo-depth = <0x40>; + status = "disabled"; }; - }; - - sysram@02020000 { - compatible = "mmio-sram"; - reg = <0x02020000 0x54000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x02020000 0x54000>; - smp-sysram@0 { - compatible = "samsung,exynos4210-sysram"; - reg = <0x0 0x1000>; + mmc_1: mmc@12210000 { + compatible = "samsung,exynos5420-dw-mshc-smu"; + interrupts = <0 76 0>; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x12210000 0x2000>; + clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>; + clock-names = "biu", "ciu"; + fifo-depth = <0x40>; + status = "disabled"; }; - smp-sysram@53000 { - compatible = "samsung,exynos4210-sysram-ns"; - reg = <0x53000 0x1000>; + mmc_2: mmc@12220000 { + compatible = "samsung,exynos5420-dw-mshc"; + interrupts = <0 77 0>; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x12220000 0x1000>; + clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>; + clock-names = "biu", "ciu"; + fifo-depth = <0x40>; + status = "disabled"; }; - }; - - clock: clock-controller@10010000 { - compatible = "samsung,exynos5420-clock"; - reg = <0x10010000 0x30000>; - #clock-cells = <1>; - }; - - clock_audss: audss-clock-controller@3810000 { - compatible = "samsung,exynos5420-audss-clock"; - reg = <0x03810000 0x0C>; - #clock-cells = <1>; - clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MAU_EPLL>, - <&clock CLK_SCLK_MAUDIO0>, <&clock CLK_SCLK_MAUPCM0>; - clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in"; - }; - - mfc: codec@11000000 { - compatible = "samsung,mfc-v7"; - reg = <0x11000000 0x10000>; - interrupts = <0 96 0>; - clocks = <&clock CLK_MFC>; - clock-names = "mfc"; - power-domains = <&mfc_pd>; - iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>; - iommu-names = "left", "right"; - }; - mmc_0: mmc@12200000 { - compatible = "samsung,exynos5420-dw-mshc-smu"; - interrupts = <0 75 0>; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x12200000 0x2000>; - clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>; - clock-names = "biu", "ciu"; - fifo-depth = <0x40>; - status = "disabled"; - }; - - mmc_1: mmc@12210000 { - compatible = "samsung,exynos5420-dw-mshc-smu"; - interrupts = <0 76 0>; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x12210000 0x2000>; - clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>; - clock-names = "biu", "ciu"; - fifo-depth = <0x40>; - status = "disabled"; - }; - - mmc_2: mmc@12220000 { - compatible = "samsung,exynos5420-dw-mshc"; - interrupts = <0 77 0>; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x12220000 0x1000>; - clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>; - clock-names = "biu", "ciu"; - fifo-depth = <0x40>; - status = "disabled"; - }; - - mct: mct@101C0000 { - compatible = "samsung,exynos4210-mct"; - reg = <0x101C0000 0x800>; - interrupt-controller; - #interrupt-cells = <1>; - interrupt-parent = <&mct_map>; - interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>, - <8>, <9>, <10>, <11>; - clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>; - clock-names = "fin_pll", "mct"; - - mct_map: mct-map { + mct: mct@101C0000 { + compatible = "samsung,exynos4210-mct"; + reg = <0x101C0000 0x800>; + interrupt-controller; #interrupt-cells = <1>; - #address-cells = <0>; - #size-cells = <0>; - interrupt-map = <0 &combiner 23 3>, - <1 &combiner 23 4>, - <2 &combiner 25 2>, - <3 &combiner 25 3>, - <4 &gic 0 120 0>, - <5 &gic 0 121 0>, - <6 &gic 0 122 0>, - <7 &gic 0 123 0>, - <8 &gic 0 128 0>, - <9 &gic 0 129 0>, - <10 &gic 0 130 0>, - <11 &gic 0 131 0>; + interrupt-parent = <&mct_map>; + interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>, + <8>, <9>, <10>, <11>; + clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>; + clock-names = "fin_pll", "mct"; + + mct_map: mct-map { + #interrupt-cells = <1>; + #address-cells = <0>; + #size-cells = <0>; + interrupt-map = <0 &combiner 23 3>, + <1 &combiner 23 4>, + <2 &combiner 25 2>, + <3 &combiner 25 3>, + <4 &gic 0 120 0>, + <5 &gic 0 121 0>, + <6 &gic 0 122 0>, + <7 &gic 0 123 0>, + <8 &gic 0 128 0>, + <9 &gic 0 129 0>, + <10 &gic 0 130 0>, + <11 &gic 0 131 0>; + }; + }; + + nocp_mem0_0: nocp@10CA1000 { + compatible = "samsung,exynos5420-nocp"; + reg = <0x10CA1000 0x200>; + status = "disabled"; }; - }; - - nocp_mem0_0: nocp@10CA1000 { - compatible = "samsung,exynos5420-nocp"; - reg = <0x10CA1000 0x200>; - status = "disabled"; - }; - - nocp_mem0_1: nocp@10CA1400 { - compatible = "samsung,exynos5420-nocp"; - reg = <0x10CA1400 0x200>; - status = "disabled"; - }; - - nocp_mem1_0: nocp@10CA1800 { - compatible = "samsung,exynos5420-nocp"; - reg = <0x10CA1800 0x200>; - status = "disabled"; - }; - - nocp_mem1_1: nocp@10CA1C00 { - compatible = "samsung,exynos5420-nocp"; - reg = <0x10CA1C00 0x200>; - status = "disabled"; - }; - - nocp_g3d_0: nocp@11A51000 { - compatible = "samsung,exynos5420-nocp"; - reg = <0x11A51000 0x200>; - status = "disabled"; - }; - - nocp_g3d_1: nocp@11A51400 { - compatible = "samsung,exynos5420-nocp"; - reg = <0x11A51400 0x200>; - status = "disabled"; - }; - - gsc_pd: power-domain@10044000 { - compatible = "samsung,exynos4210-pd"; - reg = <0x10044000 0x20>; - #power-domain-cells = <0>; - clocks = <&clock CLK_FIN_PLL>, - <&clock CLK_MOUT_USER_ACLK300_GSCL>, - <&clock CLK_GSCL0>, <&clock CLK_GSCL1>; - clock-names = "oscclk", "clk0", "asb0", "asb1"; - }; - - isp_pd: power-domain@10044020 { - compatible = "samsung,exynos4210-pd"; - reg = <0x10044020 0x20>; - #power-domain-cells = <0>; - }; - - mfc_pd: power-domain@10044060 { - compatible = "samsung,exynos4210-pd"; - reg = <0x10044060 0x20>; - clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MOUT_USER_ACLK333>; - clock-names = "oscclk", "clk0"; - #power-domain-cells = <0>; - }; - - msc_pd: power-domain@10044120 { - compatible = "samsung,exynos4210-pd"; - reg = <0x10044120 0x20>; - #power-domain-cells = <0>; - }; - - disp_pd: power-domain@100440C0 { - compatible = "samsung,exynos4210-pd"; - reg = <0x100440C0 0x20>; - #power-domain-cells = <0>; - clocks = <&clock CLK_FIN_PLL>, - <&clock CLK_MOUT_USER_ACLK200_DISP1>, - <&clock CLK_MOUT_USER_ACLK300_DISP1>, - <&clock CLK_MOUT_USER_ACLK400_DISP1>, - <&clock CLK_FIMD1>, <&clock CLK_MIXER>; - clock-names = "oscclk", "clk0", "clk1", "clk2", "asb0", "asb1"; - }; - pinctrl_0: pinctrl@13400000 { - compatible = "samsung,exynos5420-pinctrl"; - reg = <0x13400000 0x1000>; - interrupts = <0 45 0>; - - wakeup-interrupt-controller { - compatible = "samsung,exynos4210-wakeup-eint"; - interrupt-parent = <&gic>; - interrupts = <0 32 0>; + nocp_mem0_1: nocp@10CA1400 { + compatible = "samsung,exynos5420-nocp"; + reg = <0x10CA1400 0x200>; + status = "disabled"; }; - }; - - pinctrl_1: pinctrl@13410000 { - compatible = "samsung,exynos5420-pinctrl"; - reg = <0x13410000 0x1000>; - interrupts = <0 78 0>; - }; - pinctrl_2: pinctrl@14000000 { - compatible = "samsung,exynos5420-pinctrl"; - reg = <0x14000000 0x1000>; - interrupts = <0 46 0>; - }; - - pinctrl_3: pinctrl@14010000 { - compatible = "samsung,exynos5420-pinctrl"; - reg = <0x14010000 0x1000>; - interrupts = <0 50 0>; - }; - - pinctrl_4: pinctrl@03860000 { - compatible = "samsung,exynos5420-pinctrl"; - reg = <0x03860000 0x1000>; - interrupts = <0 47 0>; - }; - - amba { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - interrupt-parent = <&gic>; - ranges; - - adma: adma@03880000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x03880000 0x1000>; - interrupts = <0 110 0>; - clocks = <&clock_audss EXYNOS_ADMA>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - #dma-channels = <6>; - #dma-requests = <16>; - }; - - pdma0: pdma@121A0000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x121A0000 0x1000>; - interrupts = <0 34 0>; - clocks = <&clock CLK_PDMA0>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; - }; - - pdma1: pdma@121B0000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x121B0000 0x1000>; - interrupts = <0 35 0>; - clocks = <&clock CLK_PDMA1>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; - }; - - mdma0: mdma@10800000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x10800000 0x1000>; - interrupts = <0 33 0>; - clocks = <&clock CLK_MDMA0>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <1>; - }; - - mdma1: mdma@11C10000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x11C10000 0x1000>; - interrupts = <0 124 0>; - clocks = <&clock CLK_MDMA1>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <1>; - /* - * MDMA1 can support both secure and non-secure - * AXI transactions. When this is enabled in the kernel - * for boards that run in secure mode, we are getting - * imprecise external aborts causing the kernel to oops. - */ + nocp_mem1_0: nocp@10CA1800 { + compatible = "samsung,exynos5420-nocp"; + reg = <0x10CA1800 0x200>; status = "disabled"; }; - }; - - i2s0: i2s@03830000 { - compatible = "samsung,exynos5420-i2s"; - reg = <0x03830000 0x100>; - dmas = <&adma 0 - &adma 2 - &adma 1>; - dma-names = "tx", "rx", "tx-sec"; - clocks = <&clock_audss EXYNOS_I2S_BUS>, - <&clock_audss EXYNOS_I2S_BUS>, - <&clock_audss EXYNOS_SCLK_I2S>; - clock-names = "iis", "i2s_opclk0", "i2s_opclk1"; - #clock-cells = <1>; - clock-output-names = "i2s_cdclk0"; - #sound-dai-cells = <1>; - samsung,idma-addr = <0x03000000>; - pinctrl-names = "default"; - pinctrl-0 = <&i2s0_bus>; - status = "disabled"; - }; - - i2s1: i2s@12D60000 { - compatible = "samsung,exynos5420-i2s"; - reg = <0x12D60000 0x100>; - dmas = <&pdma1 12 - &pdma1 11>; - dma-names = "tx", "rx"; - clocks = <&clock CLK_I2S1>, <&clock CLK_SCLK_I2S1>; - clock-names = "iis", "i2s_opclk0"; - #clock-cells = <1>; - clock-output-names = "i2s_cdclk1"; - #sound-dai-cells = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&i2s1_bus>; - status = "disabled"; - }; - - i2s2: i2s@12D70000 { - compatible = "samsung,exynos5420-i2s"; - reg = <0x12D70000 0x100>; - dmas = <&pdma0 12 - &pdma0 11>; - dma-names = "tx", "rx"; - clocks = <&clock CLK_I2S2>, <&clock CLK_SCLK_I2S2>; - clock-names = "iis", "i2s_opclk0"; - #clock-cells = <1>; - clock-output-names = "i2s_cdclk2"; - #sound-dai-cells = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&i2s2_bus>; - status = "disabled"; - }; - - spi_0: spi@12d20000 { - compatible = "samsung,exynos4210-spi"; - reg = <0x12d20000 0x100>; - interrupts = <0 68 0>; - dmas = <&pdma0 5 - &pdma0 4>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&spi0_bus>; - clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>; - clock-names = "spi", "spi_busclk0"; - status = "disabled"; - }; - - spi_1: spi@12d30000 { - compatible = "samsung,exynos4210-spi"; - reg = <0x12d30000 0x100>; - interrupts = <0 69 0>; - dmas = <&pdma1 5 - &pdma1 4>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&spi1_bus>; - clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>; - clock-names = "spi", "spi_busclk0"; - status = "disabled"; - }; - - spi_2: spi@12d40000 { - compatible = "samsung,exynos4210-spi"; - reg = <0x12d40000 0x100>; - interrupts = <0 70 0>; - dmas = <&pdma0 7 - &pdma0 6>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&spi2_bus>; - clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>; - clock-names = "spi", "spi_busclk0"; - status = "disabled"; - }; - - dp_phy: dp-video-phy { - compatible = "samsung,exynos5420-dp-video-phy"; - samsung,pmu-syscon = <&pmu_system_controller>; - #phy-cells = <0>; - }; - - mipi_phy: mipi-video-phy { - compatible = "samsung,s5pv210-mipi-video-phy"; - syscon = <&pmu_system_controller>; - #phy-cells = <1>; - }; - - dsi@14500000 { - compatible = "samsung,exynos5410-mipi-dsi"; - reg = <0x14500000 0x10000>; - interrupts = <0 82 0>; - phys = <&mipi_phy 1>; - phy-names = "dsim"; - clocks = <&clock CLK_DSIM1>, <&clock CLK_SCLK_MIPI1>; - clock-names = "bus_clk", "pll_clk"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - adc: adc@12D10000 { - compatible = "samsung,exynos-adc-v2"; - reg = <0x12D10000 0x100>; - interrupts = <0 106 0>; - clocks = <&clock CLK_TSADC>; - clock-names = "adc"; - #io-channel-cells = <1>; - io-channel-ranges; - samsung,syscon-phandle = <&pmu_system_controller>; - status = "disabled"; - }; - - /* i2c_0-3 are defined in exynos5.dtsi */ - hsi2c_4: i2c@12CA0000 { - compatible = "samsung,exynos5250-hsi2c"; - reg = <0x12CA0000 0x1000>; - interrupts = <0 60 0>; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c4_hs_bus>; - clocks = <&clock CLK_USI0>; - clock-names = "hsi2c"; - status = "disabled"; - }; - - hsi2c_5: i2c@12CB0000 { - compatible = "samsung,exynos5250-hsi2c"; - reg = <0x12CB0000 0x1000>; - interrupts = <0 61 0>; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c5_hs_bus>; - clocks = <&clock CLK_USI1>; - clock-names = "hsi2c"; - status = "disabled"; - }; - - hsi2c_6: i2c@12CC0000 { - compatible = "samsung,exynos5250-hsi2c"; - reg = <0x12CC0000 0x1000>; - interrupts = <0 62 0>; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c6_hs_bus>; - clocks = <&clock CLK_USI2>; - clock-names = "hsi2c"; - status = "disabled"; - }; - - hsi2c_7: i2c@12CD0000 { - compatible = "samsung,exynos5250-hsi2c"; - reg = <0x12CD0000 0x1000>; - interrupts = <0 63 0>; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c7_hs_bus>; - clocks = <&clock CLK_USI3>; - clock-names = "hsi2c"; - status = "disabled"; - }; - - hsi2c_8: i2c@12E00000 { - compatible = "samsung,exynos5250-hsi2c"; - reg = <0x12E00000 0x1000>; - interrupts = <0 87 0>; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c8_hs_bus>; - clocks = <&clock CLK_USI4>; - clock-names = "hsi2c"; - status = "disabled"; - }; - - hsi2c_9: i2c@12E10000 { - compatible = "samsung,exynos5250-hsi2c"; - reg = <0x12E10000 0x1000>; - interrupts = <0 88 0>; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c9_hs_bus>; - clocks = <&clock CLK_USI5>; - clock-names = "hsi2c"; - status = "disabled"; - }; - - hsi2c_10: i2c@12E20000 { - compatible = "samsung,exynos5250-hsi2c"; - reg = <0x12E20000 0x1000>; - interrupts = <0 203 0>; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c10_hs_bus>; - clocks = <&clock CLK_USI6>; - clock-names = "hsi2c"; - status = "disabled"; - }; - - hdmi: hdmi@14530000 { - compatible = "samsung,exynos5420-hdmi"; - reg = <0x14530000 0x70000>; - interrupts = <0 95 0>; - clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>, - <&clock CLK_DOUT_PIXEL>, <&clock CLK_SCLK_HDMIPHY>, - <&clock CLK_MOUT_HDMI>; - clock-names = "hdmi", "sclk_hdmi", "sclk_pixel", - "sclk_hdmiphy", "mout_hdmi"; - phy = <&hdmiphy>; - samsung,syscon-phandle = <&pmu_system_controller>; - status = "disabled"; - power-domains = <&disp_pd>; - }; - - hdmiphy: hdmiphy@145D0000 { - reg = <0x145D0000 0x20>; - }; - - mixer: mixer@14450000 { - compatible = "samsung,exynos5420-mixer"; - reg = <0x14450000 0x10000>; - interrupts = <0 94 0>; - clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>, - <&clock CLK_SCLK_HDMI>; - clock-names = "mixer", "hdmi", "sclk_hdmi"; - power-domains = <&disp_pd>; - iommus = <&sysmmu_tv>; - }; - - rotator: rotator@11C00000 { - compatible = "samsung,exynos5250-rotator"; - reg = <0x11C00000 0x64>; - interrupts = <0 84 0>; - clocks = <&clock CLK_ROTATOR>; - clock-names = "rotator"; - iommus = <&sysmmu_rotator>; - }; - - gsc_0: video-scaler@13e00000 { - compatible = "samsung,exynos5-gsc"; - reg = <0x13e00000 0x1000>; - interrupts = <0 85 0>; - clocks = <&clock CLK_GSCL0>; - clock-names = "gscl"; - power-domains = <&gsc_pd>; - iommus = <&sysmmu_gscl0>; - }; - - gsc_1: video-scaler@13e10000 { - compatible = "samsung,exynos5-gsc"; - reg = <0x13e10000 0x1000>; - interrupts = <0 86 0>; - clocks = <&clock CLK_GSCL1>; - clock-names = "gscl"; - power-domains = <&gsc_pd>; - iommus = <&sysmmu_gscl1>; - }; - jpeg_0: jpeg@11F50000 { - compatible = "samsung,exynos5420-jpeg"; - reg = <0x11F50000 0x1000>; - interrupts = <0 89 0>; - clock-names = "jpeg"; - clocks = <&clock CLK_JPEG>; - iommus = <&sysmmu_jpeg0>; - }; - - jpeg_1: jpeg@11F60000 { - compatible = "samsung,exynos5420-jpeg"; - reg = <0x11F60000 0x1000>; - interrupts = <0 168 0>; - clock-names = "jpeg"; - clocks = <&clock CLK_JPEG2>; - iommus = <&sysmmu_jpeg1>; - }; - - pmu_system_controller: system-controller@10040000 { - compatible = "samsung,exynos5420-pmu", "syscon"; - reg = <0x10040000 0x5000>; - clock-names = "clkout16"; - clocks = <&clock CLK_FIN_PLL>; - #clock-cells = <1>; - interrupt-controller; - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - }; - - tmu_cpu0: tmu@10060000 { - compatible = "samsung,exynos5420-tmu"; - reg = <0x10060000 0x100>; - interrupts = <0 65 0>; - clocks = <&clock CLK_TMU>; - clock-names = "tmu_apbif"; - #include "exynos4412-tmu-sensor-conf.dtsi" - }; - - tmu_cpu1: tmu@10064000 { - compatible = "samsung,exynos5420-tmu"; - reg = <0x10064000 0x100>; - interrupts = <0 183 0>; - clocks = <&clock CLK_TMU>; - clock-names = "tmu_apbif"; - #include "exynos4412-tmu-sensor-conf.dtsi" - }; - - tmu_cpu2: tmu@10068000 { - compatible = "samsung,exynos5420-tmu-ext-triminfo"; - reg = <0x10068000 0x100>, <0x1006c000 0x4>; - interrupts = <0 184 0>; - clocks = <&clock CLK_TMU>, <&clock CLK_TMU>; - clock-names = "tmu_apbif", "tmu_triminfo_apbif"; - #include "exynos4412-tmu-sensor-conf.dtsi" - }; - - tmu_cpu3: tmu@1006c000 { - compatible = "samsung,exynos5420-tmu-ext-triminfo"; - reg = <0x1006c000 0x100>, <0x100a0000 0x4>; - interrupts = <0 185 0>; - clocks = <&clock CLK_TMU>, <&clock CLK_TMU_GPU>; - clock-names = "tmu_apbif", "tmu_triminfo_apbif"; - #include "exynos4412-tmu-sensor-conf.dtsi" - }; - - tmu_gpu: tmu@100a0000 { - compatible = "samsung,exynos5420-tmu-ext-triminfo"; - reg = <0x100a0000 0x100>, <0x10068000 0x4>; - interrupts = <0 215 0>; - clocks = <&clock CLK_TMU_GPU>, <&clock CLK_TMU>; - clock-names = "tmu_apbif", "tmu_triminfo_apbif"; - #include "exynos4412-tmu-sensor-conf.dtsi" - }; - - thermal-zones { - cpu0_thermal: cpu0-thermal { - thermal-sensors = <&tmu_cpu0>; - #include "exynos5420-trip-points.dtsi" - }; - cpu1_thermal: cpu1-thermal { - thermal-sensors = <&tmu_cpu1>; - #include "exynos5420-trip-points.dtsi" - }; - cpu2_thermal: cpu2-thermal { - thermal-sensors = <&tmu_cpu2>; - #include "exynos5420-trip-points.dtsi" - }; - cpu3_thermal: cpu3-thermal { - thermal-sensors = <&tmu_cpu3>; - #include "exynos5420-trip-points.dtsi" - }; - gpu_thermal: gpu-thermal { - thermal-sensors = <&tmu_gpu>; - #include "exynos5420-trip-points.dtsi" + nocp_mem1_1: nocp@10CA1C00 { + compatible = "samsung,exynos5420-nocp"; + reg = <0x10CA1C00 0x200>; + status = "disabled"; }; - }; - - watchdog: watchdog@101D0000 { - compatible = "samsung,exynos5420-wdt"; - reg = <0x101D0000 0x100>; - interrupts = <0 42 0>; - clocks = <&clock CLK_WDT>; - clock-names = "watchdog"; - samsung,syscon-phandle = <&pmu_system_controller>; - }; - - sss: sss@10830000 { - compatible = "samsung,exynos4210-secss"; - reg = <0x10830000 0x300>; - interrupts = <0 112 0>; - clocks = <&clock CLK_SSS>; - clock-names = "secss"; - }; - usbdrd3_0: usb3-0 { - compatible = "samsung,exynos5250-dwusb3"; - clocks = <&clock CLK_USBD300>; - clock-names = "usbdrd30"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - usbdrd_dwc3_0: dwc3@12000000 { - compatible = "snps,dwc3"; - reg = <0x12000000 0x10000>; - interrupts = <0 72 0>; - phys = <&usbdrd_phy0 0>, <&usbdrd_phy0 1>; - phy-names = "usb2-phy", "usb3-phy"; + nocp_g3d_0: nocp@11A51000 { + compatible = "samsung,exynos5420-nocp"; + reg = <0x11A51000 0x200>; + status = "disabled"; }; - }; - usbdrd_phy0: phy@12100000 { - compatible = "samsung,exynos5420-usbdrd-phy"; - reg = <0x12100000 0x100>; - clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>; - clock-names = "phy", "ref"; - samsung,pmu-syscon = <&pmu_system_controller>; - #phy-cells = <1>; - }; - - usbdrd3_1: usb3-1 { - compatible = "samsung,exynos5250-dwusb3"; - clocks = <&clock CLK_USBD301>; - clock-names = "usbdrd30"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - usbdrd_dwc3_1: dwc3@12400000 { - compatible = "snps,dwc3"; - reg = <0x12400000 0x10000>; - interrupts = <0 73 0>; - phys = <&usbdrd_phy1 0>, <&usbdrd_phy1 1>; - phy-names = "usb2-phy", "usb3-phy"; + nocp_g3d_1: nocp@11A51400 { + compatible = "samsung,exynos5420-nocp"; + reg = <0x11A51400 0x200>; + status = "disabled"; }; - }; - - usbdrd_phy1: phy@12500000 { - compatible = "samsung,exynos5420-usbdrd-phy"; - reg = <0x12500000 0x100>; - clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBPHY301>; - clock-names = "phy", "ref"; - samsung,pmu-syscon = <&pmu_system_controller>; - #phy-cells = <1>; - }; - usbhost2: usb@12110000 { - compatible = "samsung,exynos4210-ehci"; - reg = <0x12110000 0x100>; - interrupts = <0 71 0>; - - clocks = <&clock CLK_USBH20>; - clock-names = "usbhost"; - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - phys = <&usb2_phy 1>; + gsc_pd: power-domain@10044000 { + compatible = "samsung,exynos4210-pd"; + reg = <0x10044000 0x20>; + #power-domain-cells = <0>; + clocks = <&clock CLK_FIN_PLL>, + <&clock CLK_MOUT_USER_ACLK300_GSCL>, + <&clock CLK_GSCL0>, <&clock CLK_GSCL1>; + clock-names = "oscclk", "clk0", "asb0", "asb1"; }; - }; - - usbhost1: usb@12120000 { - compatible = "samsung,exynos4210-ohci"; - reg = <0x12120000 0x100>; - interrupts = <0 71 0>; - clocks = <&clock CLK_USBH20>; - clock-names = "usbhost"; - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - phys = <&usb2_phy 1>; + isp_pd: power-domain@10044020 { + compatible = "samsung,exynos4210-pd"; + reg = <0x10044020 0x20>; + #power-domain-cells = <0>; }; - }; - - usb2_phy: phy@12130000 { - compatible = "samsung,exynos5250-usb2-phy"; - reg = <0x12130000 0x100>; - clocks = <&clock CLK_USBH20>, <&clock CLK_SCLK_USBPHY300>; - clock-names = "phy", "ref"; - #phy-cells = <1>; - samsung,sysreg-phandle = <&sysreg_system_controller>; - samsung,pmureg-phandle = <&pmu_system_controller>; - }; - - sysmmu_g2dr: sysmmu@0x10A60000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x10A60000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <24 5>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>; - #iommu-cells = <0>; - }; - sysmmu_g2dw: sysmmu@0x10A70000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x10A70000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <22 2>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>; - #iommu-cells = <0>; - }; - - sysmmu_tv: sysmmu@0x14650000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x14650000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <7 4>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_MIXER>, <&clock CLK_MIXER>; - power-domains = <&disp_pd>; - #iommu-cells = <0>; - }; - - sysmmu_gscl0: sysmmu@0x13E80000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x13E80000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <2 0>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_GSCL0>, <&clock CLK_GSCL0>; - power-domains = <&gsc_pd>; - #iommu-cells = <0>; - }; - - sysmmu_gscl1: sysmmu@0x13E90000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x13E90000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <2 2>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_GSCL1>, <&clock CLK_GSCL1>; - power-domains = <&gsc_pd>; - #iommu-cells = <0>; - }; - - sysmmu_scaler0r: sysmmu@0x12880000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x12880000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <22 4>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_MSCL0>, <&clock CLK_MSCL0>; - #iommu-cells = <0>; - }; - - sysmmu_scaler1r: sysmmu@0x12890000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x12890000 0x1000>; - interrupts = <0 186 0>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_MSCL1>, <&clock CLK_MSCL1>; - #iommu-cells = <0>; - }; - - sysmmu_scaler2r: sysmmu@0x128A0000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x128A0000 0x1000>; - interrupts = <0 188 0>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_MSCL2>, <&clock CLK_MSCL2>; - #iommu-cells = <0>; - }; - - sysmmu_scaler0w: sysmmu@0x128C0000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x128C0000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <27 2>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_MSCL0>, <&clock CLK_MSCL0>; - #iommu-cells = <0>; - }; - - sysmmu_scaler1w: sysmmu@0x128D0000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x128D0000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <22 6>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_MSCL1>, <&clock CLK_MSCL1>; - #iommu-cells = <0>; - }; - - sysmmu_scaler2w: sysmmu@0x128E0000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x128E0000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <19 6>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_MSCL2>, <&clock CLK_MSCL2>; - #iommu-cells = <0>; - }; - - sysmmu_rotator: sysmmu@0x11D40000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x11D40000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <4 0>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_ROTATOR>, <&clock CLK_ROTATOR>; - #iommu-cells = <0>; - }; - - sysmmu_jpeg0: sysmmu@0x11F10000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x11F10000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <4 2>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>; - #iommu-cells = <0>; - }; - - sysmmu_jpeg1: sysmmu@0x11F20000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x11F20000 0x1000>; - interrupts = <0 169 0>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_JPEG2>, <&clock CLK_JPEG2>; - #iommu-cells = <0>; - }; - - sysmmu_mfc_l: sysmmu@0x11200000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x11200000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <6 2>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>; - power-domains = <&mfc_pd>; - #iommu-cells = <0>; - }; - - sysmmu_mfc_r: sysmmu@0x11210000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x11210000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <8 5>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>; - power-domains = <&mfc_pd>; - #iommu-cells = <0>; - }; - - sysmmu_fimd1_0: sysmmu@0x14640000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x14640000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <3 2>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_FIMD1M0>, <&clock CLK_FIMD1>; - power-domains = <&disp_pd>; - #iommu-cells = <0>; - }; - - sysmmu_fimd1_1: sysmmu@0x14680000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x14680000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <3 0>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_FIMD1M1>, <&clock CLK_FIMD1>; - power-domains = <&disp_pd>; - #iommu-cells = <0>; - }; - - bus_wcore: bus_wcore { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DOUT_ACLK400_WCORE>; - clock-names = "bus"; - operating-points-v2 = <&bus_wcore_opp_table>; - status = "disabled"; - }; - - bus_noc: bus_noc { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DOUT_ACLK100_NOC>; - clock-names = "bus"; - operating-points-v2 = <&bus_noc_opp_table>; - status = "disabled"; - }; - - bus_fsys_apb: bus_fsys_apb { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DOUT_PCLK200_FSYS>; - clock-names = "bus"; - operating-points-v2 = <&bus_fsys_apb_opp_table>; - status = "disabled"; - }; - - bus_fsys: bus_fsys { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DOUT_ACLK200_FSYS>; - clock-names = "bus"; - operating-points-v2 = <&bus_fsys_apb_opp_table>; - status = "disabled"; - }; - - bus_fsys2: bus_fsys2 { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DOUT_ACLK200_FSYS2>; - clock-names = "bus"; - operating-points-v2 = <&bus_fsys2_opp_table>; - status = "disabled"; - }; - - bus_mfc: bus_mfc { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DOUT_ACLK333>; - clock-names = "bus"; - operating-points-v2 = <&bus_mfc_opp_table>; - status = "disabled"; - }; - - bus_gen: bus_gen { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DOUT_ACLK266>; - clock-names = "bus"; - operating-points-v2 = <&bus_gen_opp_table>; - status = "disabled"; - }; - - bus_peri: bus_peri { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DOUT_ACLK66>; - clock-names = "bus"; - operating-points-v2 = <&bus_peri_opp_table>; - status = "disabled"; - }; - - bus_g2d: bus_g2d { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DOUT_ACLK333_G2D>; - clock-names = "bus"; - operating-points-v2 = <&bus_g2d_opp_table>; - status = "disabled"; - }; - - bus_g2d_acp: bus_g2d_acp { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DOUT_ACLK266_G2D>; - clock-names = "bus"; - operating-points-v2 = <&bus_g2d_acp_opp_table>; - status = "disabled"; - }; - - bus_jpeg: bus_jpeg { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DOUT_ACLK300_JPEG>; - clock-names = "bus"; - operating-points-v2 = <&bus_jpeg_opp_table>; - status = "disabled"; - }; - - bus_jpeg_apb: bus_jpeg_apb { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DOUT_ACLK166>; - clock-names = "bus"; - operating-points-v2 = <&bus_jpeg_apb_opp_table>; - status = "disabled"; - }; - - bus_disp1_fimd: bus_disp1_fimd { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DOUT_ACLK300_DISP1>; - clock-names = "bus"; - operating-points-v2 = <&bus_disp1_fimd_opp_table>; - status = "disabled"; - }; - - bus_disp1: bus_disp1 { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DOUT_ACLK400_DISP1>; - clock-names = "bus"; - operating-points-v2 = <&bus_disp1_opp_table>; - status = "disabled"; - }; - - bus_gscl_scaler: bus_gscl_scaler { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DOUT_ACLK300_GSCL>; - clock-names = "bus"; - operating-points-v2 = <&bus_gscl_opp_table>; - status = "disabled"; - }; - - bus_mscl: bus_mscl { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DOUT_ACLK400_MSCL>; - clock-names = "bus"; - operating-points-v2 = <&bus_mscl_opp_table>; - status = "disabled"; - }; - - bus_wcore_opp_table: opp_table2 { - compatible = "operating-points-v2"; - - opp00 { - opp-hz = /bits/ 64 <84000000>; - opp-microvolt = <925000>; - }; - opp01 { - opp-hz = /bits/ 64 <111000000>; - opp-microvolt = <950000>; + mfc_pd: power-domain@10044060 { + compatible = "samsung,exynos4210-pd"; + reg = <0x10044060 0x20>; + clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MOUT_USER_ACLK333>; + clock-names = "oscclk", "clk0"; + #power-domain-cells = <0>; }; - opp02 { - opp-hz = /bits/ 64 <222000000>; - opp-microvolt = <950000>; - }; - opp03 { - opp-hz = /bits/ 64 <333000000>; - opp-microvolt = <950000>; - }; - opp04 { - opp-hz = /bits/ 64 <400000000>; - opp-microvolt = <987500>; - }; - }; - - bus_noc_opp_table: opp_table3 { - compatible = "operating-points-v2"; - opp00 { - opp-hz = /bits/ 64 <67000000>; - }; - opp01 { - opp-hz = /bits/ 64 <75000000>; + msc_pd: power-domain@10044120 { + compatible = "samsung,exynos4210-pd"; + reg = <0x10044120 0x20>; + #power-domain-cells = <0>; }; - opp02 { - opp-hz = /bits/ 64 <86000000>; - }; - opp03 { - opp-hz = /bits/ 64 <100000000>; - }; - }; - bus_fsys_apb_opp_table: opp_table4 { - compatible = "operating-points-v2"; - opp-shared; - - opp00 { - opp-hz = /bits/ 64 <100000000>; - }; - opp01 { - opp-hz = /bits/ 64 <200000000>; + disp_pd: power-domain@100440C0 { + compatible = "samsung,exynos4210-pd"; + reg = <0x100440C0 0x20>; + #power-domain-cells = <0>; + clocks = <&clock CLK_FIN_PLL>, + <&clock CLK_MOUT_USER_ACLK200_DISP1>, + <&clock CLK_MOUT_USER_ACLK300_DISP1>, + <&clock CLK_MOUT_USER_ACLK400_DISP1>, + <&clock CLK_FIMD1>, <&clock CLK_MIXER>; + clock-names = "oscclk", "clk0", "clk1", "clk2", "asb0", "asb1"; }; - }; - bus_fsys2_opp_table: opp_table5 { - compatible = "operating-points-v2"; + pinctrl_0: pinctrl@13400000 { + compatible = "samsung,exynos5420-pinctrl"; + reg = <0x13400000 0x1000>; + interrupts = <0 45 0>; - opp00 { - opp-hz = /bits/ 64 <75000000>; - }; - opp01 { - opp-hz = /bits/ 64 <100000000>; - }; - opp02 { - opp-hz = /bits/ 64 <150000000>; + wakeup-interrupt-controller { + compatible = "samsung,exynos4210-wakeup-eint"; + interrupt-parent = <&gic>; + interrupts = <0 32 0>; + }; }; - }; - - bus_mfc_opp_table: opp_table6 { - compatible = "operating-points-v2"; - opp00 { - opp-hz = /bits/ 64 <96000000>; + pinctrl_1: pinctrl@13410000 { + compatible = "samsung,exynos5420-pinctrl"; + reg = <0x13410000 0x1000>; + interrupts = <0 78 0>; }; - opp01 { - opp-hz = /bits/ 64 <111000000>; + + pinctrl_2: pinctrl@14000000 { + compatible = "samsung,exynos5420-pinctrl"; + reg = <0x14000000 0x1000>; + interrupts = <0 46 0>; }; - opp02 { - opp-hz = /bits/ 64 <167000000>; + + pinctrl_3: pinctrl@14010000 { + compatible = "samsung,exynos5420-pinctrl"; + reg = <0x14010000 0x1000>; + interrupts = <0 50 0>; }; - opp03 { - opp-hz = /bits/ 64 <222000000>; + + pinctrl_4: pinctrl@03860000 { + compatible = "samsung,exynos5420-pinctrl"; + reg = <0x03860000 0x1000>; + interrupts = <0 47 0>; }; - opp04 { - opp-hz = /bits/ 64 <333000000>; + + amba { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + interrupt-parent = <&gic>; + ranges; + + adma: adma@03880000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x03880000 0x1000>; + interrupts = <0 110 0>; + clocks = <&clock_audss EXYNOS_ADMA>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + #dma-channels = <6>; + #dma-requests = <16>; + }; + + pdma0: pdma@121A0000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x121A0000 0x1000>; + interrupts = <0 34 0>; + clocks = <&clock CLK_PDMA0>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + #dma-channels = <8>; + #dma-requests = <32>; + }; + + pdma1: pdma@121B0000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x121B0000 0x1000>; + interrupts = <0 35 0>; + clocks = <&clock CLK_PDMA1>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + #dma-channels = <8>; + #dma-requests = <32>; + }; + + mdma0: mdma@10800000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x10800000 0x1000>; + interrupts = <0 33 0>; + clocks = <&clock CLK_MDMA0>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + #dma-channels = <8>; + #dma-requests = <1>; + }; + + mdma1: mdma@11C10000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x11C10000 0x1000>; + interrupts = <0 124 0>; + clocks = <&clock CLK_MDMA1>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + #dma-channels = <8>; + #dma-requests = <1>; + /* + * MDMA1 can support both secure and non-secure + * AXI transactions. When this is enabled in + * the kernel for boards that run in secure + * mode, we are getting imprecise external + * aborts causing the kernel to oops. + */ + status = "disabled"; + }; + }; + + i2s0: i2s@03830000 { + compatible = "samsung,exynos5420-i2s"; + reg = <0x03830000 0x100>; + dmas = <&adma 0 + &adma 2 + &adma 1>; + dma-names = "tx", "rx", "tx-sec"; + clocks = <&clock_audss EXYNOS_I2S_BUS>, + <&clock_audss EXYNOS_I2S_BUS>, + <&clock_audss EXYNOS_SCLK_I2S>; + clock-names = "iis", "i2s_opclk0", "i2s_opclk1"; + #clock-cells = <1>; + clock-output-names = "i2s_cdclk0"; + #sound-dai-cells = <1>; + samsung,idma-addr = <0x03000000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_bus>; + status = "disabled"; }; - }; - bus_gen_opp_table: opp_table7 { - compatible = "operating-points-v2"; + i2s1: i2s@12D60000 { + compatible = "samsung,exynos5420-i2s"; + reg = <0x12D60000 0x100>; + dmas = <&pdma1 12 + &pdma1 11>; + dma-names = "tx", "rx"; + clocks = <&clock CLK_I2S1>, <&clock CLK_SCLK_I2S1>; + clock-names = "iis", "i2s_opclk0"; + #clock-cells = <1>; + clock-output-names = "i2s_cdclk1"; + #sound-dai-cells = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1_bus>; + status = "disabled"; + }; - opp00 { - opp-hz = /bits/ 64 <89000000>; + i2s2: i2s@12D70000 { + compatible = "samsung,exynos5420-i2s"; + reg = <0x12D70000 0x100>; + dmas = <&pdma0 12 + &pdma0 11>; + dma-names = "tx", "rx"; + clocks = <&clock CLK_I2S2>, <&clock CLK_SCLK_I2S2>; + clock-names = "iis", "i2s_opclk0"; + #clock-cells = <1>; + clock-output-names = "i2s_cdclk2"; + #sound-dai-cells = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s2_bus>; + status = "disabled"; }; - opp01 { - opp-hz = /bits/ 64 <133000000>; + + spi_0: spi@12d20000 { + compatible = "samsung,exynos4210-spi"; + reg = <0x12d20000 0x100>; + interrupts = <0 68 0>; + dmas = <&pdma0 5 + &pdma0 4>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&spi0_bus>; + clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>; + clock-names = "spi", "spi_busclk0"; + status = "disabled"; }; - opp02 { - opp-hz = /bits/ 64 <178000000>; + + spi_1: spi@12d30000 { + compatible = "samsung,exynos4210-spi"; + reg = <0x12d30000 0x100>; + interrupts = <0 69 0>; + dmas = <&pdma1 5 + &pdma1 4>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&spi1_bus>; + clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>; + clock-names = "spi", "spi_busclk0"; + status = "disabled"; }; - opp03 { - opp-hz = /bits/ 64 <267000000>; + + spi_2: spi@12d40000 { + compatible = "samsung,exynos4210-spi"; + reg = <0x12d40000 0x100>; + interrupts = <0 70 0>; + dmas = <&pdma0 7 + &pdma0 6>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&spi2_bus>; + clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>; + clock-names = "spi", "spi_busclk0"; + status = "disabled"; }; - }; - bus_peri_opp_table: opp_table8 { - compatible = "operating-points-v2"; + dp_phy: dp-video-phy { + compatible = "samsung,exynos5420-dp-video-phy"; + samsung,pmu-syscon = <&pmu_system_controller>; + #phy-cells = <0>; + }; - opp00 { - opp-hz = /bits/ 64 <67000000>; + mipi_phy: mipi-video-phy { + compatible = "samsung,s5pv210-mipi-video-phy"; + syscon = <&pmu_system_controller>; + #phy-cells = <1>; }; - }; - bus_g2d_opp_table: opp_table9 { - compatible = "operating-points-v2"; + dsi@14500000 { + compatible = "samsung,exynos5410-mipi-dsi"; + reg = <0x14500000 0x10000>; + interrupts = <0 82 0>; + phys = <&mipi_phy 1>; + phy-names = "dsim"; + clocks = <&clock CLK_DSIM1>, <&clock CLK_SCLK_MIPI1>; + clock-names = "bus_clk", "pll_clk"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; - opp00 { - opp-hz = /bits/ 64 <84000000>; + adc: adc@12D10000 { + compatible = "samsung,exynos-adc-v2"; + reg = <0x12D10000 0x100>; + interrupts = <0 106 0>; + clocks = <&clock CLK_TSADC>; + clock-names = "adc"; + #io-channel-cells = <1>; + io-channel-ranges; + samsung,syscon-phandle = <&pmu_system_controller>; + status = "disabled"; }; - opp01 { - opp-hz = /bits/ 64 <167000000>; + + /* i2c_0-3 are defined in exynos5.dtsi */ + hsi2c_4: i2c@12CA0000 { + compatible = "samsung,exynos5250-hsi2c"; + reg = <0x12CA0000 0x1000>; + interrupts = <0 60 0>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_hs_bus>; + clocks = <&clock CLK_USI0>; + clock-names = "hsi2c"; + status = "disabled"; }; - opp02 { - opp-hz = /bits/ 64 <222000000>; + + hsi2c_5: i2c@12CB0000 { + compatible = "samsung,exynos5250-hsi2c"; + reg = <0x12CB0000 0x1000>; + interrupts = <0 61 0>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c5_hs_bus>; + clocks = <&clock CLK_USI1>; + clock-names = "hsi2c"; + status = "disabled"; }; - opp03 { - opp-hz = /bits/ 64 <300000000>; + + hsi2c_6: i2c@12CC0000 { + compatible = "samsung,exynos5250-hsi2c"; + reg = <0x12CC0000 0x1000>; + interrupts = <0 62 0>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c6_hs_bus>; + clocks = <&clock CLK_USI2>; + clock-names = "hsi2c"; + status = "disabled"; }; - opp04 { - opp-hz = /bits/ 64 <333000000>; + + hsi2c_7: i2c@12CD0000 { + compatible = "samsung,exynos5250-hsi2c"; + reg = <0x12CD0000 0x1000>; + interrupts = <0 63 0>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c7_hs_bus>; + clocks = <&clock CLK_USI3>; + clock-names = "hsi2c"; + status = "disabled"; }; - }; - bus_g2d_acp_opp_table: opp_table10 { - compatible = "operating-points-v2"; + hsi2c_8: i2c@12E00000 { + compatible = "samsung,exynos5250-hsi2c"; + reg = <0x12E00000 0x1000>; + interrupts = <0 87 0>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c8_hs_bus>; + clocks = <&clock CLK_USI4>; + clock-names = "hsi2c"; + status = "disabled"; + }; - opp00 { - opp-hz = /bits/ 64 <67000000>; + hsi2c_9: i2c@12E10000 { + compatible = "samsung,exynos5250-hsi2c"; + reg = <0x12E10000 0x1000>; + interrupts = <0 88 0>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c9_hs_bus>; + clocks = <&clock CLK_USI5>; + clock-names = "hsi2c"; + status = "disabled"; }; - opp01 { - opp-hz = /bits/ 64 <133000000>; + + hsi2c_10: i2c@12E20000 { + compatible = "samsung,exynos5250-hsi2c"; + reg = <0x12E20000 0x1000>; + interrupts = <0 203 0>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c10_hs_bus>; + clocks = <&clock CLK_USI6>; + clock-names = "hsi2c"; + status = "disabled"; }; - opp02 { - opp-hz = /bits/ 64 <178000000>; + + hdmi: hdmi@14530000 { + compatible = "samsung,exynos5420-hdmi"; + reg = <0x14530000 0x70000>; + interrupts = <0 95 0>; + clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>, + <&clock CLK_DOUT_PIXEL>, <&clock CLK_SCLK_HDMIPHY>, + <&clock CLK_MOUT_HDMI>; + clock-names = "hdmi", "sclk_hdmi", "sclk_pixel", + "sclk_hdmiphy", "mout_hdmi"; + phy = <&hdmiphy>; + samsung,syscon-phandle = <&pmu_system_controller>; + status = "disabled"; + power-domains = <&disp_pd>; + }; + + hdmiphy: hdmiphy@145D0000 { + reg = <0x145D0000 0x20>; + }; + + mixer: mixer@14450000 { + compatible = "samsung,exynos5420-mixer"; + reg = <0x14450000 0x10000>; + interrupts = <0 94 0>; + clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>, + <&clock CLK_SCLK_HDMI>; + clock-names = "mixer", "hdmi", "sclk_hdmi"; + power-domains = <&disp_pd>; + iommus = <&sysmmu_tv>; + }; + + rotator: rotator@11C00000 { + compatible = "samsung,exynos5250-rotator"; + reg = <0x11C00000 0x64>; + interrupts = <0 84 0>; + clocks = <&clock CLK_ROTATOR>; + clock-names = "rotator"; + iommus = <&sysmmu_rotator>; + }; + + gsc_0: video-scaler@13e00000 { + compatible = "samsung,exynos5-gsc"; + reg = <0x13e00000 0x1000>; + interrupts = <0 85 0>; + clocks = <&clock CLK_GSCL0>; + clock-names = "gscl"; + power-domains = <&gsc_pd>; + iommus = <&sysmmu_gscl0>; + }; + + gsc_1: video-scaler@13e10000 { + compatible = "samsung,exynos5-gsc"; + reg = <0x13e10000 0x1000>; + interrupts = <0 86 0>; + clocks = <&clock CLK_GSCL1>; + clock-names = "gscl"; + power-domains = <&gsc_pd>; + iommus = <&sysmmu_gscl1>; + }; + + jpeg_0: jpeg@11F50000 { + compatible = "samsung,exynos5420-jpeg"; + reg = <0x11F50000 0x1000>; + interrupts = <0 89 0>; + clock-names = "jpeg"; + clocks = <&clock CLK_JPEG>; + iommus = <&sysmmu_jpeg0>; + }; + + jpeg_1: jpeg@11F60000 { + compatible = "samsung,exynos5420-jpeg"; + reg = <0x11F60000 0x1000>; + interrupts = <0 168 0>; + clock-names = "jpeg"; + clocks = <&clock CLK_JPEG2>; + iommus = <&sysmmu_jpeg1>; + }; + + pmu_system_controller: system-controller@10040000 { + compatible = "samsung,exynos5420-pmu", "syscon"; + reg = <0x10040000 0x5000>; + clock-names = "clkout16"; + clocks = <&clock CLK_FIN_PLL>; + #clock-cells = <1>; + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; }; - opp03 { - opp-hz = /bits/ 64 <267000000>; + + tmu_cpu0: tmu@10060000 { + compatible = "samsung,exynos5420-tmu"; + reg = <0x10060000 0x100>; + interrupts = <0 65 0>; + clocks = <&clock CLK_TMU>; + clock-names = "tmu_apbif"; + #include "exynos4412-tmu-sensor-conf.dtsi" + }; + + tmu_cpu1: tmu@10064000 { + compatible = "samsung,exynos5420-tmu"; + reg = <0x10064000 0x100>; + interrupts = <0 183 0>; + clocks = <&clock CLK_TMU>; + clock-names = "tmu_apbif"; + #include "exynos4412-tmu-sensor-conf.dtsi" + }; + + tmu_cpu2: tmu@10068000 { + compatible = "samsung,exynos5420-tmu-ext-triminfo"; + reg = <0x10068000 0x100>, <0x1006c000 0x4>; + interrupts = <0 184 0>; + clocks = <&clock CLK_TMU>, <&clock CLK_TMU>; + clock-names = "tmu_apbif", "tmu_triminfo_apbif"; + #include "exynos4412-tmu-sensor-conf.dtsi" + }; + + tmu_cpu3: tmu@1006c000 { + compatible = "samsung,exynos5420-tmu-ext-triminfo"; + reg = <0x1006c000 0x100>, <0x100a0000 0x4>; + interrupts = <0 185 0>; + clocks = <&clock CLK_TMU>, <&clock CLK_TMU_GPU>; + clock-names = "tmu_apbif", "tmu_triminfo_apbif"; + #include "exynos4412-tmu-sensor-conf.dtsi" + }; + + tmu_gpu: tmu@100a0000 { + compatible = "samsung,exynos5420-tmu-ext-triminfo"; + reg = <0x100a0000 0x100>, <0x10068000 0x4>; + interrupts = <0 215 0>; + clocks = <&clock CLK_TMU_GPU>, <&clock CLK_TMU>; + clock-names = "tmu_apbif", "tmu_triminfo_apbif"; + #include "exynos4412-tmu-sensor-conf.dtsi" + }; + + watchdog: watchdog@101D0000 { + compatible = "samsung,exynos5420-wdt"; + reg = <0x101D0000 0x100>; + interrupts = <0 42 0>; + clocks = <&clock CLK_WDT>; + clock-names = "watchdog"; + samsung,syscon-phandle = <&pmu_system_controller>; + }; + + sss: sss@10830000 { + compatible = "samsung,exynos4210-secss"; + reg = <0x10830000 0x300>; + interrupts = <0 112 0>; + clocks = <&clock CLK_SSS>; + clock-names = "secss"; + }; + + usbdrd3_0: usb3-0 { + compatible = "samsung,exynos5250-dwusb3"; + clocks = <&clock CLK_USBD300>; + clock-names = "usbdrd30"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + usbdrd_dwc3_0: dwc3@12000000 { + compatible = "snps,dwc3"; + reg = <0x12000000 0x10000>; + interrupts = <0 72 0>; + phys = <&usbdrd_phy0 0>, <&usbdrd_phy0 1>; + phy-names = "usb2-phy", "usb3-phy"; + }; + }; + + usbdrd_phy0: phy@12100000 { + compatible = "samsung,exynos5420-usbdrd-phy"; + reg = <0x12100000 0x100>; + clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>; + clock-names = "phy", "ref"; + samsung,pmu-syscon = <&pmu_system_controller>; + #phy-cells = <1>; + }; + + usbdrd3_1: usb3-1 { + compatible = "samsung,exynos5250-dwusb3"; + clocks = <&clock CLK_USBD301>; + clock-names = "usbdrd30"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + usbdrd_dwc3_1: dwc3@12400000 { + compatible = "snps,dwc3"; + reg = <0x12400000 0x10000>; + interrupts = <0 73 0>; + phys = <&usbdrd_phy1 0>, <&usbdrd_phy1 1>; + phy-names = "usb2-phy", "usb3-phy"; + }; + }; + + usbdrd_phy1: phy@12500000 { + compatible = "samsung,exynos5420-usbdrd-phy"; + reg = <0x12500000 0x100>; + clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBPHY301>; + clock-names = "phy", "ref"; + samsung,pmu-syscon = <&pmu_system_controller>; + #phy-cells = <1>; + }; + + usbhost2: usb@12110000 { + compatible = "samsung,exynos4210-ehci"; + reg = <0x12110000 0x100>; + interrupts = <0 71 0>; + + clocks = <&clock CLK_USBH20>; + clock-names = "usbhost"; + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + phys = <&usb2_phy 1>; + }; }; - }; - bus_jpeg_opp_table: opp_table11 { - compatible = "operating-points-v2"; + usbhost1: usb@12120000 { + compatible = "samsung,exynos4210-ohci"; + reg = <0x12120000 0x100>; + interrupts = <0 71 0>; - opp00 { - opp-hz = /bits/ 64 <75000000>; - }; - opp01 { - opp-hz = /bits/ 64 <150000000>; - }; - opp02 { - opp-hz = /bits/ 64 <200000000>; - }; - opp03 { - opp-hz = /bits/ 64 <300000000>; + clocks = <&clock CLK_USBH20>; + clock-names = "usbhost"; + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + phys = <&usb2_phy 1>; + }; + }; + + usb2_phy: phy@12130000 { + compatible = "samsung,exynos5250-usb2-phy"; + reg = <0x12130000 0x100>; + clocks = <&clock CLK_USBH20>, <&clock CLK_SCLK_USBPHY300>; + clock-names = "phy", "ref"; + #phy-cells = <1>; + samsung,sysreg-phandle = <&sysreg_system_controller>; + samsung,pmureg-phandle = <&pmu_system_controller>; + }; + + sysmmu_g2dr: sysmmu@0x10A60000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x10A60000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <24 5>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>; + #iommu-cells = <0>; + }; + + sysmmu_g2dw: sysmmu@0x10A70000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x10A70000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <22 2>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>; + #iommu-cells = <0>; + }; + + sysmmu_tv: sysmmu@0x14650000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x14650000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <7 4>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_MIXER>, <&clock CLK_MIXER>; + power-domains = <&disp_pd>; + #iommu-cells = <0>; + }; + + sysmmu_gscl0: sysmmu@0x13E80000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x13E80000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <2 0>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_GSCL0>, <&clock CLK_GSCL0>; + power-domains = <&gsc_pd>; + #iommu-cells = <0>; + }; + + sysmmu_gscl1: sysmmu@0x13E90000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x13E90000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <2 2>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_GSCL1>, <&clock CLK_GSCL1>; + power-domains = <&gsc_pd>; + #iommu-cells = <0>; + }; + + sysmmu_scaler0r: sysmmu@0x12880000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x12880000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <22 4>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_MSCL0>, <&clock CLK_MSCL0>; + #iommu-cells = <0>; + }; + + sysmmu_scaler1r: sysmmu@0x12890000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x12890000 0x1000>; + interrupts = <0 186 0>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_MSCL1>, <&clock CLK_MSCL1>; + #iommu-cells = <0>; + }; + + sysmmu_scaler2r: sysmmu@0x128A0000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x128A0000 0x1000>; + interrupts = <0 188 0>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_MSCL2>, <&clock CLK_MSCL2>; + #iommu-cells = <0>; + }; + + sysmmu_scaler0w: sysmmu@0x128C0000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x128C0000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <27 2>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_MSCL0>, <&clock CLK_MSCL0>; + #iommu-cells = <0>; + }; + + sysmmu_scaler1w: sysmmu@0x128D0000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x128D0000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <22 6>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_MSCL1>, <&clock CLK_MSCL1>; + #iommu-cells = <0>; + }; + + sysmmu_scaler2w: sysmmu@0x128E0000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x128E0000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <19 6>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_MSCL2>, <&clock CLK_MSCL2>; + #iommu-cells = <0>; + }; + + sysmmu_rotator: sysmmu@0x11D40000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x11D40000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <4 0>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_ROTATOR>, <&clock CLK_ROTATOR>; + #iommu-cells = <0>; + }; + + sysmmu_jpeg0: sysmmu@0x11F10000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x11F10000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <4 2>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>; + #iommu-cells = <0>; + }; + + sysmmu_jpeg1: sysmmu@0x11F20000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x11F20000 0x1000>; + interrupts = <0 169 0>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_JPEG2>, <&clock CLK_JPEG2>; + #iommu-cells = <0>; + }; + + sysmmu_mfc_l: sysmmu@0x11200000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x11200000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <6 2>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>; + power-domains = <&mfc_pd>; + #iommu-cells = <0>; + }; + + sysmmu_mfc_r: sysmmu@0x11210000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x11210000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <8 5>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>; + power-domains = <&mfc_pd>; + #iommu-cells = <0>; + }; + + sysmmu_fimd1_0: sysmmu@0x14640000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x14640000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <3 2>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_FIMD1M0>, <&clock CLK_FIMD1>; + power-domains = <&disp_pd>; + #iommu-cells = <0>; + }; + + sysmmu_fimd1_1: sysmmu@0x14680000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x14680000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <3 0>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_FIMD1M1>, <&clock CLK_FIMD1>; + power-domains = <&disp_pd>; + #iommu-cells = <0>; + }; + + bus_wcore: bus_wcore { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DOUT_ACLK400_WCORE>; + clock-names = "bus"; + operating-points-v2 = <&bus_wcore_opp_table>; + status = "disabled"; }; - }; - bus_jpeg_apb_opp_table: opp_table12 { - compatible = "operating-points-v2"; + bus_noc: bus_noc { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DOUT_ACLK100_NOC>; + clock-names = "bus"; + operating-points-v2 = <&bus_noc_opp_table>; + status = "disabled"; + }; - opp00 { - opp-hz = /bits/ 64 <84000000>; + bus_fsys_apb: bus_fsys_apb { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DOUT_PCLK200_FSYS>; + clock-names = "bus"; + operating-points-v2 = <&bus_fsys_apb_opp_table>; + status = "disabled"; }; - opp01 { - opp-hz = /bits/ 64 <111000000>; + + bus_fsys: bus_fsys { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DOUT_ACLK200_FSYS>; + clock-names = "bus"; + operating-points-v2 = <&bus_fsys_apb_opp_table>; + status = "disabled"; }; - opp02 { - opp-hz = /bits/ 64 <134000000>; + + bus_fsys2: bus_fsys2 { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DOUT_ACLK200_FSYS2>; + clock-names = "bus"; + operating-points-v2 = <&bus_fsys2_opp_table>; + status = "disabled"; }; - opp03 { - opp-hz = /bits/ 64 <167000000>; + + bus_mfc: bus_mfc { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DOUT_ACLK333>; + clock-names = "bus"; + operating-points-v2 = <&bus_mfc_opp_table>; + status = "disabled"; }; - }; - bus_disp1_fimd_opp_table: opp_table13 { - compatible = "operating-points-v2"; + bus_gen: bus_gen { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DOUT_ACLK266>; + clock-names = "bus"; + operating-points-v2 = <&bus_gen_opp_table>; + status = "disabled"; + }; - opp00 { - opp-hz = /bits/ 64 <120000000>; + bus_peri: bus_peri { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DOUT_ACLK66>; + clock-names = "bus"; + operating-points-v2 = <&bus_peri_opp_table>; + status = "disabled"; }; - opp01 { - opp-hz = /bits/ 64 <200000000>; + + bus_g2d: bus_g2d { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DOUT_ACLK333_G2D>; + clock-names = "bus"; + operating-points-v2 = <&bus_g2d_opp_table>; + status = "disabled"; }; - }; - bus_disp1_opp_table: opp_table14 { - compatible = "operating-points-v2"; + bus_g2d_acp: bus_g2d_acp { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DOUT_ACLK266_G2D>; + clock-names = "bus"; + operating-points-v2 = <&bus_g2d_acp_opp_table>; + status = "disabled"; + }; - opp00 { - opp-hz = /bits/ 64 <120000000>; + bus_jpeg: bus_jpeg { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DOUT_ACLK300_JPEG>; + clock-names = "bus"; + operating-points-v2 = <&bus_jpeg_opp_table>; + status = "disabled"; }; - opp01 { - opp-hz = /bits/ 64 <200000000>; + + bus_jpeg_apb: bus_jpeg_apb { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DOUT_ACLK166>; + clock-names = "bus"; + operating-points-v2 = <&bus_jpeg_apb_opp_table>; + status = "disabled"; }; - opp02 { - opp-hz = /bits/ 64 <300000000>; + + bus_disp1_fimd: bus_disp1_fimd { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DOUT_ACLK300_DISP1>; + clock-names = "bus"; + operating-points-v2 = <&bus_disp1_fimd_opp_table>; + status = "disabled"; }; - }; - bus_gscl_opp_table: opp_table15 { - compatible = "operating-points-v2"; + bus_disp1: bus_disp1 { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DOUT_ACLK400_DISP1>; + clock-names = "bus"; + operating-points-v2 = <&bus_disp1_opp_table>; + status = "disabled"; + }; - opp00 { - opp-hz = /bits/ 64 <150000000>; + bus_gscl_scaler: bus_gscl_scaler { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DOUT_ACLK300_GSCL>; + clock-names = "bus"; + operating-points-v2 = <&bus_gscl_opp_table>; + status = "disabled"; }; - opp01 { - opp-hz = /bits/ 64 <200000000>; + + bus_mscl: bus_mscl { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DOUT_ACLK400_MSCL>; + clock-names = "bus"; + operating-points-v2 = <&bus_mscl_opp_table>; + status = "disabled"; }; - opp02 { - opp-hz = /bits/ 64 <300000000>; + + bus_wcore_opp_table: opp_table2 { + compatible = "operating-points-v2"; + + opp00 { + opp-hz = /bits/ 64 <84000000>; + opp-microvolt = <925000>; + }; + opp01 { + opp-hz = /bits/ 64 <111000000>; + opp-microvolt = <950000>; + }; + opp02 { + opp-hz = /bits/ 64 <222000000>; + opp-microvolt = <950000>; + }; + opp03 { + opp-hz = /bits/ 64 <333000000>; + opp-microvolt = <950000>; + }; + opp04 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <987500>; + }; + }; + + bus_noc_opp_table: opp_table3 { + compatible = "operating-points-v2"; + + opp00 { + opp-hz = /bits/ 64 <67000000>; + }; + opp01 { + opp-hz = /bits/ 64 <75000000>; + }; + opp02 { + opp-hz = /bits/ 64 <86000000>; + }; + opp03 { + opp-hz = /bits/ 64 <100000000>; + }; + }; + + bus_fsys_apb_opp_table: opp_table4 { + compatible = "operating-points-v2"; + opp-shared; + + opp00 { + opp-hz = /bits/ 64 <100000000>; + }; + opp01 { + opp-hz = /bits/ 64 <200000000>; + }; + }; + + bus_fsys2_opp_table: opp_table5 { + compatible = "operating-points-v2"; + + opp00 { + opp-hz = /bits/ 64 <75000000>; + }; + opp01 { + opp-hz = /bits/ 64 <100000000>; + }; + opp02 { + opp-hz = /bits/ 64 <150000000>; + }; + }; + + bus_mfc_opp_table: opp_table6 { + compatible = "operating-points-v2"; + + opp00 { + opp-hz = /bits/ 64 <96000000>; + }; + opp01 { + opp-hz = /bits/ 64 <111000000>; + }; + opp02 { + opp-hz = /bits/ 64 <167000000>; + }; + opp03 { + opp-hz = /bits/ 64 <222000000>; + }; + opp04 { + opp-hz = /bits/ 64 <333000000>; + }; + }; + + bus_gen_opp_table: opp_table7 { + compatible = "operating-points-v2"; + + opp00 { + opp-hz = /bits/ 64 <89000000>; + }; + opp01 { + opp-hz = /bits/ 64 <133000000>; + }; + opp02 { + opp-hz = /bits/ 64 <178000000>; + }; + opp03 { + opp-hz = /bits/ 64 <267000000>; + }; + }; + + bus_peri_opp_table: opp_table8 { + compatible = "operating-points-v2"; + + opp00 { + opp-hz = /bits/ 64 <67000000>; + }; + }; + + bus_g2d_opp_table: opp_table9 { + compatible = "operating-points-v2"; + + opp00 { + opp-hz = /bits/ 64 <84000000>; + }; + opp01 { + opp-hz = /bits/ 64 <167000000>; + }; + opp02 { + opp-hz = /bits/ 64 <222000000>; + }; + opp03 { + opp-hz = /bits/ 64 <300000000>; + }; + opp04 { + opp-hz = /bits/ 64 <333000000>; + }; + }; + + bus_g2d_acp_opp_table: opp_table10 { + compatible = "operating-points-v2"; + + opp00 { + opp-hz = /bits/ 64 <67000000>; + }; + opp01 { + opp-hz = /bits/ 64 <133000000>; + }; + opp02 { + opp-hz = /bits/ 64 <178000000>; + }; + opp03 { + opp-hz = /bits/ 64 <267000000>; + }; + }; + + bus_jpeg_opp_table: opp_table11 { + compatible = "operating-points-v2"; + + opp00 { + opp-hz = /bits/ 64 <75000000>; + }; + opp01 { + opp-hz = /bits/ 64 <150000000>; + }; + opp02 { + opp-hz = /bits/ 64 <200000000>; + }; + opp03 { + opp-hz = /bits/ 64 <300000000>; + }; + }; + + bus_jpeg_apb_opp_table: opp_table12 { + compatible = "operating-points-v2"; + + opp00 { + opp-hz = /bits/ 64 <84000000>; + }; + opp01 { + opp-hz = /bits/ 64 <111000000>; + }; + opp02 { + opp-hz = /bits/ 64 <134000000>; + }; + opp03 { + opp-hz = /bits/ 64 <167000000>; + }; + }; + + bus_disp1_fimd_opp_table: opp_table13 { + compatible = "operating-points-v2"; + + opp00 { + opp-hz = /bits/ 64 <120000000>; + }; + opp01 { + opp-hz = /bits/ 64 <200000000>; + }; + }; + + bus_disp1_opp_table: opp_table14 { + compatible = "operating-points-v2"; + + opp00 { + opp-hz = /bits/ 64 <120000000>; + }; + opp01 { + opp-hz = /bits/ 64 <200000000>; + }; + opp02 { + opp-hz = /bits/ 64 <300000000>; + }; + }; + + bus_gscl_opp_table: opp_table15 { + compatible = "operating-points-v2"; + + opp00 { + opp-hz = /bits/ 64 <150000000>; + }; + opp01 { + opp-hz = /bits/ 64 <200000000>; + }; + opp02 { + opp-hz = /bits/ 64 <300000000>; + }; + }; + + bus_mscl_opp_table: opp_table16 { + compatible = "operating-points-v2"; + + opp00 { + opp-hz = /bits/ 64 <84000000>; + }; + opp01 { + opp-hz = /bits/ 64 <167000000>; + }; + opp02 { + opp-hz = /bits/ 64 <222000000>; + }; + opp03 { + opp-hz = /bits/ 64 <333000000>; + }; + opp04 { + opp-hz = /bits/ 64 <400000000>; + }; }; }; - bus_mscl_opp_table: opp_table16 { - compatible = "operating-points-v2"; - - opp00 { - opp-hz = /bits/ 64 <84000000>; + thermal-zones { + cpu0_thermal: cpu0-thermal { + thermal-sensors = <&tmu_cpu0>; + #include "exynos5420-trip-points.dtsi" }; - opp01 { - opp-hz = /bits/ 64 <167000000>; + cpu1_thermal: cpu1-thermal { + thermal-sensors = <&tmu_cpu1>; + #include "exynos5420-trip-points.dtsi" }; - opp02 { - opp-hz = /bits/ 64 <222000000>; + cpu2_thermal: cpu2-thermal { + thermal-sensors = <&tmu_cpu2>; + #include "exynos5420-trip-points.dtsi" }; - opp03 { - opp-hz = /bits/ 64 <333000000>; + cpu3_thermal: cpu3-thermal { + thermal-sensors = <&tmu_cpu3>; + #include "exynos5420-trip-points.dtsi" }; - opp04 { - opp-hz = /bits/ 64 <400000000>; + gpu_thermal: gpu-thermal { + thermal-sensors = <&tmu_gpu>; + #include "exynos5420-trip-points.dtsi" }; }; }; -- cgit v1.2.1 From 3f2f95ff6aa3490ae57364424b59b80cbff6be29 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 8 May 2016 18:41:57 +0200 Subject: ARM: dts: exynos: MCT is not an interrupt controller and extend length of iomap Multi-Core Timer generates interrupts but it is not really an interrupt controller so remove the "interrupt-controller" and "interrupt-cells" properties. Additionally extend the length of mapped memory to cover all registers (last SFR is at 0x0A40). Signed-off-by: Krzysztof Kozlowski Reviewed-by: Javier Martinez Canillas Tested-by: Javier Martinez Canillas --- arch/arm/boot/dts/exynos5420.dtsi | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'arch/arm/boot/dts/exynos5420.dtsi') diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index b65bdbe2e563..fa8bda836cef 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -263,9 +263,7 @@ mct: mct@101C0000 { compatible = "samsung,exynos4210-mct"; - reg = <0x101C0000 0x800>; - interrupt-controller; - #interrupt-cells = <1>; + reg = <0x101C0000 0xB00>; interrupt-parent = <&mct_map>; interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>, <8>, <9>, <10>, <11>; -- cgit v1.2.1 From c9cf996d854b8f96d450083d3e0aace457a5a46b Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 8 May 2016 18:41:57 +0200 Subject: ARM: dts: exynos: Move common Exynos5410/542x/5800 nodes to new DTSI The Exynos5410/542x/5800 are very similar designs. Create a new DTSI with common nodes to remove DTS duplication. Although currently only MCT and SysRAM are shared but in future more nodes will be added to the common file. The patch should not have functional impact. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Javier Martinez Canillas Tested-by: Javier Martinez Canillas --- arch/arm/boot/dts/exynos5420.dtsi | 54 +++++---------------------------------- 1 file changed, 6 insertions(+), 48 deletions(-) (limited to 'arch/arm/boot/dts/exynos5420.dtsi') diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index fa8bda836cef..2d9f43b8cc15 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -13,9 +13,8 @@ * published by the Free Software Foundation. */ +#include "exynos54xx.dtsi" #include -#include "exynos5.dtsi" - #include / { @@ -181,24 +180,6 @@ }; }; - sysram@02020000 { - compatible = "mmio-sram"; - reg = <0x02020000 0x54000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x02020000 0x54000>; - - smp-sysram@0 { - compatible = "samsung,exynos4210-sysram"; - reg = <0x0 0x1000>; - }; - - smp-sysram@53000 { - compatible = "samsung,exynos4210-sysram-ns"; - reg = <0x53000 0x1000>; - }; - }; - clock: clock-controller@10010000 { compatible = "samsung,exynos5420-clock"; reg = <0x10010000 0x30000>; @@ -261,34 +242,6 @@ status = "disabled"; }; - mct: mct@101C0000 { - compatible = "samsung,exynos4210-mct"; - reg = <0x101C0000 0xB00>; - interrupt-parent = <&mct_map>; - interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>, - <8>, <9>, <10>, <11>; - clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>; - clock-names = "fin_pll", "mct"; - - mct_map: mct-map { - #interrupt-cells = <1>; - #address-cells = <0>; - #size-cells = <0>; - interrupt-map = <0 &combiner 23 3>, - <1 &combiner 23 4>, - <2 &combiner 25 2>, - <3 &combiner 25 3>, - <4 &gic 0 120 0>, - <5 &gic 0 121 0>, - <6 &gic 0 122 0>, - <7 &gic 0 123 0>, - <8 &gic 0 128 0>, - <9 &gic 0 129 0>, - <10 &gic 0 130 0>, - <11 &gic 0 131 0>; - }; - }; - nocp_mem0_0: nocp@10CA1000 { compatible = "samsung,exynos5420-nocp"; reg = <0x10CA1000 0x200>; @@ -1570,6 +1523,11 @@ pinctrl-0 = <&i2c3_bus>; }; +&mct { + clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>; + clock-names = "fin_pll", "mct"; +}; + &pwm { clocks = <&clock CLK_PWM>; clock-names = "timers"; -- cgit v1.2.1 From cb0896562228703209644e92926ed445150cc594 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 8 May 2016 19:42:11 +0200 Subject: ARM: dts: exynos: Add USB to Exynos5410 Move USB 3.0 DWC and 2.0 EHCI/OHCI nodes from exynos5420.dtsi to exynos54xx.dtsi common for entire family. For Exynos542x/5800 this should not have functional impact but for Exynos5410 this effectively adds USB support. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Javier Martinez Canillas Tested-by: Javier Martinez Canillas --- arch/arm/boot/dts/exynos5420.dtsi | 133 +++++++++++--------------------------- 1 file changed, 39 insertions(+), 94 deletions(-) (limited to 'arch/arm/boot/dts/exynos5420.dtsi') diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index 2d9f43b8cc15..64450f555c14 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -41,8 +41,6 @@ spi0 = &spi_0; spi1 = &spi_1; spi2 = &spi_2; - usbdrdphy0 = &usbdrd_phy0; - usbdrdphy1 = &usbdrd_phy1; }; /* @@ -806,98 +804,6 @@ clock-names = "secss"; }; - usbdrd3_0: usb3-0 { - compatible = "samsung,exynos5250-dwusb3"; - clocks = <&clock CLK_USBD300>; - clock-names = "usbdrd30"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - usbdrd_dwc3_0: dwc3@12000000 { - compatible = "snps,dwc3"; - reg = <0x12000000 0x10000>; - interrupts = <0 72 0>; - phys = <&usbdrd_phy0 0>, <&usbdrd_phy0 1>; - phy-names = "usb2-phy", "usb3-phy"; - }; - }; - - usbdrd_phy0: phy@12100000 { - compatible = "samsung,exynos5420-usbdrd-phy"; - reg = <0x12100000 0x100>; - clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>; - clock-names = "phy", "ref"; - samsung,pmu-syscon = <&pmu_system_controller>; - #phy-cells = <1>; - }; - - usbdrd3_1: usb3-1 { - compatible = "samsung,exynos5250-dwusb3"; - clocks = <&clock CLK_USBD301>; - clock-names = "usbdrd30"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - usbdrd_dwc3_1: dwc3@12400000 { - compatible = "snps,dwc3"; - reg = <0x12400000 0x10000>; - interrupts = <0 73 0>; - phys = <&usbdrd_phy1 0>, <&usbdrd_phy1 1>; - phy-names = "usb2-phy", "usb3-phy"; - }; - }; - - usbdrd_phy1: phy@12500000 { - compatible = "samsung,exynos5420-usbdrd-phy"; - reg = <0x12500000 0x100>; - clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBPHY301>; - clock-names = "phy", "ref"; - samsung,pmu-syscon = <&pmu_system_controller>; - #phy-cells = <1>; - }; - - usbhost2: usb@12110000 { - compatible = "samsung,exynos4210-ehci"; - reg = <0x12110000 0x100>; - interrupts = <0 71 0>; - - clocks = <&clock CLK_USBH20>; - clock-names = "usbhost"; - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - phys = <&usb2_phy 1>; - }; - }; - - usbhost1: usb@12120000 { - compatible = "samsung,exynos4210-ohci"; - reg = <0x12120000 0x100>; - interrupts = <0 71 0>; - - clocks = <&clock CLK_USBH20>; - clock-names = "usbhost"; - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - phys = <&usb2_phy 1>; - }; - }; - - usb2_phy: phy@12130000 { - compatible = "samsung,exynos5250-usb2-phy"; - reg = <0x12130000 0x100>; - clocks = <&clock CLK_USBH20>, <&clock CLK_SCLK_USBPHY300>; - clock-names = "phy", "ref"; - #phy-cells = <1>; - samsung,sysreg-phandle = <&sysreg_system_controller>; - samsung,pmureg-phandle = <&pmu_system_controller>; - }; - sysmmu_g2dr: sysmmu@0x10A60000 { compatible = "samsung,exynos-sysmmu"; reg = <0x10A60000 0x1000>; @@ -1560,4 +1466,43 @@ clock-names = "uart", "clk_uart_baud0"; }; +&usbdrd3_0 { + clocks = <&clock CLK_USBD300>; + clock-names = "usbdrd30"; +}; + +&usbdrd_phy0 { + clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>; + clock-names = "phy", "ref"; + samsung,pmu-syscon = <&pmu_system_controller>; +}; + +&usbdrd3_1 { + clocks = <&clock CLK_USBD301>; + clock-names = "usbdrd30"; +}; + +&usbdrd_phy1 { + clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBPHY301>; + clock-names = "phy", "ref"; + samsung,pmu-syscon = <&pmu_system_controller>; +}; + +&usbhost1 { + clocks = <&clock CLK_USBH20>; + clock-names = "usbhost"; +}; + +&usbhost2 { + clocks = <&clock CLK_USBH20>; + clock-names = "usbhost"; +}; + +&usb2_phy { + clocks = <&clock CLK_USBH20>, <&clock CLK_SCLK_USBPHY300>; + clock-names = "phy", "ref"; + samsung,sysreg-phandle = <&sysreg_system_controller>; + samsung,pmureg-phandle = <&pmu_system_controller>; +}; + #include "exynos5420-pinctrl.dtsi" -- cgit v1.2.1 From 538fc7ad51b85bff727a147947300406a5ad220f Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 10 May 2016 20:17:23 +0200 Subject: ARM: dts: exynos: Move HSI2C nodes to exynos54xx.dtsi The USI/HSI2C nodes can be mostly shared between Exynos5420 and Exynos5410 so move them to common DTSI. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Javier Martinez Canillas Tested-by: Javier Martinez Canillas --- arch/arm/boot/dts/exynos5420.dtsi | 85 +++++++++++++-------------------------- 1 file changed, 28 insertions(+), 57 deletions(-) (limited to 'arch/arm/boot/dts/exynos5420.dtsi') diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index 64450f555c14..8196194f0758 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -29,10 +29,6 @@ pinctrl2 = &pinctrl_2; pinctrl3 = &pinctrl_3; pinctrl4 = &pinctrl_4; - i2c4 = &hsi2c_4; - i2c5 = &hsi2c_5; - i2c6 = &hsi2c_6; - i2c7 = &hsi2c_7; i2c8 = &hsi2c_8; i2c9 = &hsi2c_9; i2c10 = &hsi2c_10; @@ -562,59 +558,6 @@ status = "disabled"; }; - /* i2c_0-3 are defined in exynos5.dtsi */ - hsi2c_4: i2c@12CA0000 { - compatible = "samsung,exynos5250-hsi2c"; - reg = <0x12CA0000 0x1000>; - interrupts = <0 60 0>; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c4_hs_bus>; - clocks = <&clock CLK_USI0>; - clock-names = "hsi2c"; - status = "disabled"; - }; - - hsi2c_5: i2c@12CB0000 { - compatible = "samsung,exynos5250-hsi2c"; - reg = <0x12CB0000 0x1000>; - interrupts = <0 61 0>; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c5_hs_bus>; - clocks = <&clock CLK_USI1>; - clock-names = "hsi2c"; - status = "disabled"; - }; - - hsi2c_6: i2c@12CC0000 { - compatible = "samsung,exynos5250-hsi2c"; - reg = <0x12CC0000 0x1000>; - interrupts = <0 62 0>; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c6_hs_bus>; - clocks = <&clock CLK_USI2>; - clock-names = "hsi2c"; - status = "disabled"; - }; - - hsi2c_7: i2c@12CD0000 { - compatible = "samsung,exynos5250-hsi2c"; - reg = <0x12CD0000 0x1000>; - interrupts = <0 63 0>; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c7_hs_bus>; - clocks = <&clock CLK_USI3>; - clock-names = "hsi2c"; - status = "disabled"; - }; - hsi2c_8: i2c@12E00000 { compatible = "samsung,exynos5250-hsi2c"; reg = <0x12E00000 0x1000>; @@ -1429,6 +1372,34 @@ pinctrl-0 = <&i2c3_bus>; }; +&hsi2c_4 { + clocks = <&clock CLK_USI0>; + clock-names = "hsi2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_hs_bus>; +}; + +&hsi2c_5 { + clocks = <&clock CLK_USI1>; + clock-names = "hsi2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c5_hs_bus>; +}; + +&hsi2c_6 { + clocks = <&clock CLK_USI2>; + clock-names = "hsi2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c6_hs_bus>; +}; + +&hsi2c_7 { + clocks = <&clock CLK_USI3>; + clock-names = "hsi2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c7_hs_bus>; +}; + &mct { clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>; clock-names = "fin_pll", "mct"; -- cgit v1.2.1 From e5995e6df69e2652d923bbe33174676166b10787 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 31 May 2016 20:39:02 +0200 Subject: ARM: dts: exynos: Interrupt for USB DWC3-1 differs between Exynos5420 and 5410 On Exynos5410 the SPI interrupt for second USB DWC3 (called DRD: Dual Role Device) is different - 200 instead of 73. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Javier Martinez Canillas Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos5420.dtsi | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm/boot/dts/exynos5420.dtsi') diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index 8196194f0758..b036b46a6281 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -16,6 +16,7 @@ #include "exynos54xx.dtsi" #include #include +#include / { compatible = "samsung,exynos5420", "samsung,exynos5"; @@ -1453,6 +1454,10 @@ clock-names = "usbdrd30"; }; +&usbdrd_dwc3_1 { + interrupts = ; +}; + &usbdrd_phy1 { clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBPHY301>; clock-names = "phy", "ref"; -- cgit v1.2.1 From b8bd7e23bb0be762c39510497c931066dc62e62f Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 1 Jun 2016 11:45:51 +0200 Subject: ARM: dts: exynos: Add watchdog and Security SubSystem to Exynos5410 Move watchdog and Security SubSystem nodes from exynos5420.dtsi to file shared with Exynos5410 and configure the clocks on the latter. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Javier Martinez Canillas --- arch/arm/boot/dts/exynos5420.dtsi | 28 +++++++++++----------------- 1 file changed, 11 insertions(+), 17 deletions(-) (limited to 'arch/arm/boot/dts/exynos5420.dtsi') diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index b036b46a6281..fa306a182083 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -731,23 +731,6 @@ #include "exynos4412-tmu-sensor-conf.dtsi" }; - watchdog: watchdog@101D0000 { - compatible = "samsung,exynos5420-wdt"; - reg = <0x101D0000 0x100>; - interrupts = <0 42 0>; - clocks = <&clock CLK_WDT>; - clock-names = "watchdog"; - samsung,syscon-phandle = <&pmu_system_controller>; - }; - - sss: sss@10830000 { - compatible = "samsung,exynos4210-secss"; - reg = <0x10830000 0x300>; - interrupts = <0 112 0>; - clocks = <&clock CLK_SSS>; - clock-names = "secss"; - }; - sysmmu_g2dr: sysmmu@0x10A60000 { compatible = "samsung,exynos-sysmmu"; reg = <0x10A60000 0x1000>; @@ -1438,6 +1421,11 @@ clock-names = "uart", "clk_uart_baud0"; }; +&sss { + clocks = <&clock CLK_SSS>; + clock-names = "secss"; +}; + &usbdrd3_0 { clocks = <&clock CLK_USBD300>; clock-names = "usbdrd30"; @@ -1481,4 +1469,10 @@ samsung,pmureg-phandle = <&pmu_system_controller>; }; +&watchdog { + clocks = <&clock CLK_WDT>; + clock-names = "watchdog"; + samsung,syscon-phandle = <&pmu_system_controller>; +}; + #include "exynos5420-pinctrl.dtsi" -- cgit v1.2.1