From 2998b1d3b1ee31e1c21085383226be1b0c496eab Mon Sep 17 00:00:00 2001 From: Roland Stigge Date: Wed, 7 Nov 2012 13:30:50 +0100 Subject: ARM: LPC32xx: Remove superfluous irq_alloc_descs() This patch removes the call to irq_alloc_descs() which always returns an error since the descriptors are always preallocated already. Signed-off-by: Roland Stigge --- arch/arm/mach-lpc32xx/irq.c | 10 +--------- 1 file changed, 1 insertion(+), 9 deletions(-) (limited to 'arch/arm/mach-lpc32xx') diff --git a/arch/arm/mach-lpc32xx/irq.c b/arch/arm/mach-lpc32xx/irq.c index 3c6332753358..54c68b12bae0 100644 --- a/arch/arm/mach-lpc32xx/irq.c +++ b/arch/arm/mach-lpc32xx/irq.c @@ -412,7 +412,6 @@ static const struct of_device_id mic_of_match[] __initconst = { void __init lpc32xx_init_irq(void) { unsigned int i; - int irq_base; /* Setup MIC */ __raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_MIC_BASE)); @@ -475,15 +474,8 @@ void __init lpc32xx_init_irq(void) of_irq_init(mic_of_match); - irq_base = irq_alloc_descs(-1, 0, NR_IRQS, 0); - if (irq_base < 0) { - pr_warn("Cannot allocate irq_descs, assuming pre-allocated\n"); - irq_base = 0; - } - lpc32xx_mic_domain = irq_domain_add_legacy(lpc32xx_mic_np, NR_IRQS, - irq_base, 0, - &irq_domain_simple_ops, + 0, 0, &irq_domain_simple_ops, NULL); if (!lpc32xx_mic_domain) panic("Unable to add MIC irq domain\n"); -- cgit v1.2.1 From e40ec953b6ac21257760730af8c36e2695e4beac Mon Sep 17 00:00:00 2001 From: Roland Stigge Date: Wed, 7 Nov 2012 13:30:50 +0100 Subject: ARM: LPC32xx: Relocate calls to irq_set_chained_handler() This patch fixes the issue of an access to a yet uninitialized data structure at the point where irq_set_chained_handler() was called by moving the respective calls to the end of lpc32xx_init_irq(). The call path was: irq_set_chained_handler() -> __irq_set_handler() -> irq_startup() -> irq_enable() -> desc->irq_data.chip->irq_unmask() at which point lpc32xx_unmask_irq() effectively read desc->irq_data.hwirq which was only later initialized. Signed-off-by: Roland Stigge --- arch/arm/mach-lpc32xx/irq.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'arch/arm/mach-lpc32xx') diff --git a/arch/arm/mach-lpc32xx/irq.c b/arch/arm/mach-lpc32xx/irq.c index 54c68b12bae0..f06229687026 100644 --- a/arch/arm/mach-lpc32xx/irq.c +++ b/arch/arm/mach-lpc32xx/irq.c @@ -447,10 +447,6 @@ void __init lpc32xx_init_irq(void) __raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_SIC1_BASE)); __raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_SIC2_BASE)); - /* MIC SUBIRQx interrupts will route handling to the chain handlers */ - irq_set_chained_handler(IRQ_LPC32XX_SUB1IRQ, lpc32xx_sic1_handler); - irq_set_chained_handler(IRQ_LPC32XX_SUB2IRQ, lpc32xx_sic2_handler); - /* Initially disable all wake events */ __raw_writel(0, LPC32XX_CLKPWR_P01_ER); __raw_writel(0, LPC32XX_CLKPWR_INT_ER); @@ -479,4 +475,8 @@ void __init lpc32xx_init_irq(void) NULL); if (!lpc32xx_mic_domain) panic("Unable to add MIC irq domain\n"); + + /* MIC SUBIRQx interrupts will route handling to the chain handlers */ + irq_set_chained_handler(IRQ_LPC32XX_SUB1IRQ, lpc32xx_sic1_handler); + irq_set_chained_handler(IRQ_LPC32XX_SUB2IRQ, lpc32xx_sic2_handler); } -- cgit v1.2.1 From 91deef8069e7ffafac4467200e1d37af1b2d7c56 Mon Sep 17 00:00:00 2001 From: Roland Stigge Date: Wed, 7 Nov 2012 13:30:50 +0100 Subject: ARM: LPC32xx: Cleanup irq.c This patch removes the IRQ mask initialization which is already done some lines above. This was actually a bug: The init was supposed to set the bits for the (chained) SUB IRQs. But this is already fixed by the previous patch, doing this implicitely via irq_set_chained_handler(). Signed-off-by: Roland Stigge --- arch/arm/mach-lpc32xx/irq.c | 5 ----- 1 file changed, 5 deletions(-) (limited to 'arch/arm/mach-lpc32xx') diff --git a/arch/arm/mach-lpc32xx/irq.c b/arch/arm/mach-lpc32xx/irq.c index f06229687026..9ecb8f9c4ef5 100644 --- a/arch/arm/mach-lpc32xx/irq.c +++ b/arch/arm/mach-lpc32xx/irq.c @@ -442,11 +442,6 @@ void __init lpc32xx_init_irq(void) lpc32xx_set_default_mappings(SIC1_APR_DEFAULT, SIC1_ATR_DEFAULT, 32); lpc32xx_set_default_mappings(SIC2_APR_DEFAULT, SIC2_ATR_DEFAULT, 64); - /* mask all interrupts except SUBIRQ */ - __raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_MIC_BASE)); - __raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_SIC1_BASE)); - __raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_SIC2_BASE)); - /* Initially disable all wake events */ __raw_writel(0, LPC32XX_CLKPWR_P01_ER); __raw_writel(0, LPC32XX_CLKPWR_INT_ER); -- cgit v1.2.1 From 84cee34db4d34b9059f4ef66f7d1805e438cc7f3 Mon Sep 17 00:00:00 2001 From: Alban Bedel Date: Mon, 12 Nov 2012 11:27:40 +0100 Subject: ARM: LPC32xx: Add the motor PWM clock --- arch/arm/mach-lpc32xx/clock.c | 8 ++++++++ arch/arm/mach-lpc32xx/include/mach/platform.h | 1 + 2 files changed, 9 insertions(+) (limited to 'arch/arm/mach-lpc32xx') diff --git a/arch/arm/mach-lpc32xx/clock.c b/arch/arm/mach-lpc32xx/clock.c index f48c2e961b84..dd5d6f532e8c 100644 --- a/arch/arm/mach-lpc32xx/clock.c +++ b/arch/arm/mach-lpc32xx/clock.c @@ -585,6 +585,13 @@ static struct clk clk_timer3 = { .enable_mask = LPC32XX_CLKPWR_TMRPWMCLK_TIMER3_EN, .get_rate = local_return_parent_rate, }; +static struct clk clk_mpwm = { + .parent = &clk_pclk, + .enable = local_onoff_enable, + .enable_reg = LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1, + .enable_mask = LPC32XX_CLKPWR_TMRPWMCLK_MPWM_EN, + .get_rate = local_return_parent_rate, +}; static struct clk clk_wdt = { .parent = &clk_pclk, .enable = local_onoff_enable, @@ -1202,6 +1209,7 @@ static struct clk_lookup lookups[] = { CLKDEV_INIT("pl08xdmac", NULL, &clk_dma), CLKDEV_INIT("4003c000.watchdog", NULL, &clk_wdt), CLKDEV_INIT("4005c000.pwm", NULL, &clk_pwm), + CLKDEV_INIT("400e8000.mpwm", NULL, &clk_mpwm), CLKDEV_INIT(NULL, "uart3_ck", &clk_uart3), CLKDEV_INIT(NULL, "uart4_ck", &clk_uart4), CLKDEV_INIT(NULL, "uart5_ck", &clk_uart5), diff --git a/arch/arm/mach-lpc32xx/include/mach/platform.h b/arch/arm/mach-lpc32xx/include/mach/platform.h index acc4aabf1c7b..b5612a1d1839 100644 --- a/arch/arm/mach-lpc32xx/include/mach/platform.h +++ b/arch/arm/mach-lpc32xx/include/mach/platform.h @@ -515,6 +515,7 @@ /* * clkpwr_timers_pwms_clk_ctrl_1 register definitions */ +#define LPC32XX_CLKPWR_TMRPWMCLK_MPWM_EN 0x40 #define LPC32XX_CLKPWR_TMRPWMCLK_TIMER3_EN 0x20 #define LPC32XX_CLKPWR_TMRPWMCLK_TIMER2_EN 0x10 #define LPC32XX_CLKPWR_TMRPWMCLK_TIMER1_EN 0x08 -- cgit v1.2.1