From 28342c6113dcfb1c730dff71c7ac0feab5ee2e6a Mon Sep 17 00:00:00 2001 From: Richard Zhao Date: Fri, 14 Sep 2012 14:42:45 +0800 Subject: ARM: dts: imx6q-sabrelite: add usbmisc device - add usbmisc device - set property fsl,usbmisc for usb controllers - set disable-over-current for imx6q-sabrelite usb otg Signed-off-by: Richard Zhao Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6q-sabrelite.dts | 1 + arch/arm/boot/dts/imx6q.dtsi | 11 +++++++++++ 2 files changed, 12 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx6q-sabrelite.dts b/arch/arm/boot/dts/imx6q-sabrelite.dts index 0fb29ca7a9e1..0cb7dcd63c9e 100644 --- a/arch/arm/boot/dts/imx6q-sabrelite.dts +++ b/arch/arm/boot/dts/imx6q-sabrelite.dts @@ -68,6 +68,7 @@ aips-bus@02100000 { /* AIPS2 */ usb@02184000 { /* USB OTG */ vbus-supply = <®_usb_otg_vbus>; + disable-over-current; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi index e45476dc6d32..b40c0ddd2648 100644 --- a/arch/arm/boot/dts/imx6q.dtsi +++ b/arch/arm/boot/dts/imx6q.dtsi @@ -777,6 +777,7 @@ interrupts = <0 43 0x04>; clocks = <&clks 162>; fsl,usbphy = <&usbphy1>; + fsl,usbmisc = <&usbmisc 0>; status = "disabled"; }; @@ -786,6 +787,7 @@ interrupts = <0 40 0x04>; clocks = <&clks 162>; fsl,usbphy = <&usbphy2>; + fsl,usbmisc = <&usbmisc 1>; status = "disabled"; }; @@ -794,6 +796,7 @@ reg = <0x02184400 0x200>; interrupts = <0 41 0x04>; clocks = <&clks 162>; + fsl,usbmisc = <&usbmisc 2>; status = "disabled"; }; @@ -802,9 +805,17 @@ reg = <0x02184600 0x200>; interrupts = <0 42 0x04>; clocks = <&clks 162>; + fsl,usbmisc = <&usbmisc 3>; status = "disabled"; }; + usbmisc: usbmisc@02184800 { + #index-cells = <1>; + compatible = "fsl,imx6q-usbmisc"; + reg = <0x02184800 0x200>; + clocks = <&clks 162>; + }; + ethernet@02188000 { compatible = "fsl,imx6q-fec"; reg = <0x02188000 0x4000>; -- cgit v1.2.1 From 97a53092a148e6c70aabf13835143cc3dd4b524c Mon Sep 17 00:00:00 2001 From: Richard Zhao Date: Wed, 19 Sep 2012 11:25:16 +0800 Subject: ARM: dts: imx6q-sabrelite: add usbotg pinctrl support Signed-off-by: Richard Zhao Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6q-sabrelite.dts | 2 ++ arch/arm/boot/dts/imx6q.dtsi | 8 ++++++++ 2 files changed, 10 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx6q-sabrelite.dts b/arch/arm/boot/dts/imx6q-sabrelite.dts index 0cb7dcd63c9e..d152328285a1 100644 --- a/arch/arm/boot/dts/imx6q-sabrelite.dts +++ b/arch/arm/boot/dts/imx6q-sabrelite.dts @@ -68,6 +68,8 @@ aips-bus@02100000 { /* AIPS2 */ usb@02184000 { /* USB OTG */ vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg_1>; disable-over-current; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi index b40c0ddd2648..35e5895ba3df 100644 --- a/arch/arm/boot/dts/imx6q.dtsi +++ b/arch/arm/boot/dts/imx6q.dtsi @@ -661,6 +661,14 @@ }; }; + usbotg { + pinctrl_usbotg_1: usbotggrp-1 { + fsl,pins = < + 1592 0x17059 /* MX6Q_PAD_GPIO_1__ANATOP_USBOTG_ID */ + >; + }; + }; + usdhc2 { pinctrl_usdhc2_1: usdhc2grp-1 { fsl,pins = < -- cgit v1.2.1 From cc7887c3b1a08d3900160d93df4ddda5fa7f725b Mon Sep 17 00:00:00 2001 From: Huang Shijie Date: Mon, 10 Sep 2012 15:17:56 +0800 Subject: ARM: imx6q: use pll2_pfd2_396m as the enfc_sel's parent The gpmi-nand driver can support the ONFI nand chip's EDO (extra data out) mode in the asynchrounous mode. In the asynchrounous mode 5, the gpmi needs 100MHz clock for the IO. But with the pll2_pfd0_352m, we can not get the 100MHz clock. So choose pll2_pfd2_396m as enfc_sel's parent. Signed-off-by: Huang Shijie Signed-off-by: Shawn Guo --- arch/arm/mach-imx/clk-imx6q.c | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c index bbc71f57b92b..744327fc5e2b 100644 --- a/arch/arm/mach-imx/clk-imx6q.c +++ b/arch/arm/mach-imx/clk-imx6q.c @@ -404,6 +404,13 @@ int __init mx6q_clocks_init(void) clk_register_clkdev(clk[ahb], "ahb", NULL); clk_register_clkdev(clk[cko1], "cko1", NULL); + /* + * The gpmi needs 100MHz frequency in the EDO/Sync mode, + * We can not get the 100MHz from the pll2_pfd0_352m. + * So choose pll2_pfd2_396m as enfc_sel's parent. + */ + clk_set_parent(clk[enfc_sel], clk[pll2_pfd2_396m]); + for (i = 0; i < ARRAY_SIZE(clks_init_on); i++) clk_prepare_enable(clk[clks_init_on[i]]); -- cgit v1.2.1