From efe4a1acdc2c70da9025cf405112667e5580a572 Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Fri, 2 Jun 2017 12:29:58 -0700 Subject: MIPS: SEAD-3: Remove GIC timer from DT The SEAD-3 board doesn't & never has configured the GIC frequency. Remove the timer node from the DT in order to avoid attempting to probe the GIC clocksource/clockevent driver which will produce error messages such as these during boot: [ 0.000000] GIC frequency not specified. [ 0.000000] Failed to initialize '/interrupt-controller@1b1c0000/timer': -22 [ 0.000000] clocksource_probe: no matching clocksources found Signed-off-by: Paul Burton Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/16188/ Signed-off-by: Ralf Baechle --- arch/mips/boot/dts/mti/sead3.dts | 5 ----- 1 file changed, 5 deletions(-) (limited to 'arch/mips/boot/dts') diff --git a/arch/mips/boot/dts/mti/sead3.dts b/arch/mips/boot/dts/mti/sead3.dts index b112879a5d9d..1bf58f841bbb 100644 --- a/arch/mips/boot/dts/mti/sead3.dts +++ b/arch/mips/boot/dts/mti/sead3.dts @@ -54,11 +54,6 @@ * controller & should be probed first. */ interrupt-parent = <&cpu_intc>; - - timer { - compatible = "mti,gic-timer"; - interrupts = ; - }; }; ehci@1b200000 { -- cgit v1.2.1 From c3d62fc6a058d1024f3ad0525a251e9d6c5203ed Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Fri, 2 Jun 2017 12:29:53 -0700 Subject: MIPS: generic/yamon-dt: Use serial* rather than uart* aliases Name aliases in the SEAD-3 device tree serial0 & serial1, rather than uart0 & uart1. This allows the core serial code to make use of the aliases to ensure that the UARTs are consistently numbered as expected rather than having the numbering depend upon probe order. When translating YAMON-provided serial configuration to a device tree stdout-path property adjust accordingly, such that we continue to reference a valid alias. Signed-off-by: Paul Burton Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/16183/ Signed-off-by: Ralf Baechle --- arch/mips/boot/dts/mti/sead3.dts | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/mips/boot/dts') diff --git a/arch/mips/boot/dts/mti/sead3.dts b/arch/mips/boot/dts/mti/sead3.dts index 1bf58f841bbb..f327791cbcb5 100644 --- a/arch/mips/boot/dts/mti/sead3.dts +++ b/arch/mips/boot/dts/mti/sead3.dts @@ -14,12 +14,12 @@ interrupt-parent = <&gic>; chosen { - stdout-path = "uart1:115200"; + stdout-path = "serial1:115200"; }; aliases { - uart0 = &uart0; - uart1 = &uart1; + serial0 = &uart0; + serial1 = &uart1; }; cpus { -- cgit v1.2.1 From fbdc674ba33c3791b315a546019e570e3e94e599 Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Fri, 2 Jun 2017 12:29:57 -0700 Subject: MIPS: SEAD-3: Set interrupt-parent per-device, not at root node The SEAD-3 board may be configured with or without a MIPS Global Interrupt Controller (GIC). Because of this we have a device tree with a default case of a GIC present, and code to fixup the device tree based upon a configuration register that indicates the presence of the GIC. In order to keep this DT fixup code simple, the interrupt-parent property was specified at the root node of the SEAD-3 DT, allowing the fixup code to simply change this property to the phandle of the CPU interrupt controller if a GIC is not present & affect all interrupt-using devices at once. This however causes a problem if we do have a GIC & the device tree is used as-is, because the interrupt-parent property of the root node applies to the CPU interrupt controller node. This causes a cycle when of_irq_init() attempts to probe interrupt controllers in order and boots fail due to a lack of configured interrupts, with this message printed on the kernel console: [ 0.000000] OF: of_irq_init: children remain, but no parents Fix this by removing the interrupt-parent property from the DT root node & instead setting it for each device which uses interrupts, ensuring that the CPU interrupt controller node has no interrupt-parent & allowing of_irq_init() to identify it as the root interrupt controller. Signed-off-by: Paul Burton Reported-by: Keng Koh Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/16187/ Signed-off-by: Ralf Baechle --- arch/mips/boot/dts/mti/sead3.dts | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'arch/mips/boot/dts') diff --git a/arch/mips/boot/dts/mti/sead3.dts b/arch/mips/boot/dts/mti/sead3.dts index f327791cbcb5..cabe256f9a68 100644 --- a/arch/mips/boot/dts/mti/sead3.dts +++ b/arch/mips/boot/dts/mti/sead3.dts @@ -11,7 +11,6 @@ #size-cells = <1>; compatible = "mti,sead-3"; model = "MIPS SEAD-3"; - interrupt-parent = <&gic>; chosen { stdout-path = "serial1:115200"; @@ -60,6 +59,7 @@ compatible = "generic-ehci"; reg = <0x1b200000 0x1000>; + interrupt-parent = <&gic>; interrupts = <0>; /* GIC 0 or CPU 6 */ has-transaction-translator; @@ -222,6 +222,7 @@ clock-frequency = <14745600>; + interrupt-parent = <&gic>; interrupts = <3>; /* GIC 3 or CPU 4 */ no-loopback-test; @@ -236,6 +237,7 @@ clock-frequency = <14745600>; + interrupt-parent = <&gic>; interrupts = <2>; /* GIC 2 or CPU 4 */ no-loopback-test; @@ -246,6 +248,7 @@ reg = <0x1f010000 0x10000>; reg-io-width = <4>; + interrupt-parent = <&gic>; interrupts = <0>; /* GIC 0 or CPU 6 */ phy-mode = "mii"; -- cgit v1.2.1 From d3f616346def161cfb0e4153692713f066755639 Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Fri, 2 Jun 2017 12:29:59 -0700 Subject: MIPS: SEAD-3: Fix GIC interrupt specifiers The various interrupt specifiers in the device tree are not in a valid format for the MIPS GIC interrupt controller binding. Where each interrupt should provide 3 values - GIC_LOCAL or GIC_SHARED, the pin number & the type of interrupt - the device tree was only providing the pin number. This causes interrupts for those devices to not be used when a GIC is present. SEAD-3 systems without a GIC are unaffected since the DT fixup code generates interrupt specifiers that are valid for the CPU interrupt controller. Fix this by adding the GIC_SHARED & IRQ_TYPE_LEVEL_HIGH values to each interrupt specifier. Signed-off-by: Paul Burton Fixes: c11e3b48dbc3 ("MIPS: SEAD3: Probe UARTs using DT") Fixes: a34e93882de4 ("MIPS: SEAD3: Probe ethernet controller using DT") Fixes: 7afd2a5aec2e ("MIPS: SEAD3: Probe EHCI controller using DT") Cc: linux-mips@linux-mips.org Cc: stable@vger.kernel.org # v4.9+ Patchwork: https://patchwork.linux-mips.org/patch/16189/ Signed-off-by: Ralf Baechle --- arch/mips/boot/dts/mti/sead3.dts | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'arch/mips/boot/dts') diff --git a/arch/mips/boot/dts/mti/sead3.dts b/arch/mips/boot/dts/mti/sead3.dts index cabe256f9a68..4f8bc83c2960 100644 --- a/arch/mips/boot/dts/mti/sead3.dts +++ b/arch/mips/boot/dts/mti/sead3.dts @@ -60,7 +60,7 @@ reg = <0x1b200000 0x1000>; interrupt-parent = <&gic>; - interrupts = <0>; /* GIC 0 or CPU 6 */ + interrupts = ; /* GIC 0 or CPU 6 */ has-transaction-translator; }; @@ -223,7 +223,7 @@ clock-frequency = <14745600>; interrupt-parent = <&gic>; - interrupts = <3>; /* GIC 3 or CPU 4 */ + interrupts = ; /* GIC 3 or CPU 4 */ no-loopback-test; }; @@ -238,7 +238,7 @@ clock-frequency = <14745600>; interrupt-parent = <&gic>; - interrupts = <2>; /* GIC 2 or CPU 4 */ + interrupts = ; /* GIC 2 or CPU 4 */ no-loopback-test; }; @@ -249,7 +249,7 @@ reg-io-width = <4>; interrupt-parent = <&gic>; - interrupts = <0>; /* GIC 0 or CPU 6 */ + interrupts = ; /* GIC 0 or CPU 6 */ phy-mode = "mii"; smsc,irq-push-pull; -- cgit v1.2.1 From 4d2804b7d76ef6e6cd85be74999548276d23067f Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Sat, 17 Jun 2017 13:52:48 -0700 Subject: MIPS: DTS: img: Don't attempt to build-in all .dtb files When building a FIT image we may want the kernel to build multiple .dtb files, but we don't want to build them all into the kernel binary as object files since they'll instead be included in the FIT image. Commit daa10170da27 ("MIPS: DTS: img: add device tree for Marduk board") however created arch/mips/boot/dts/img/Makefile with a line that builds any enabled .dtb files into the kernel. Remove this & build the pistachio object specifically, in preparation for adding .dtb targets which we don't want to build into the kernel. Signed-off-by: Paul Burton Cc: Rahul Bedarkar Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/16484/ Signed-off-by: Ralf Baechle --- arch/mips/boot/dts/img/Makefile | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'arch/mips/boot/dts') diff --git a/arch/mips/boot/dts/img/Makefile b/arch/mips/boot/dts/img/Makefile index 69a65f0f82d2..c178cf56f5b8 100644 --- a/arch/mips/boot/dts/img/Makefile +++ b/arch/mips/boot/dts/img/Makefile @@ -1,6 +1,5 @@ dtb-$(CONFIG_MACH_PISTACHIO) += pistachio_marduk.dtb - -obj-y += $(patsubst %.dtb, %.dtb.o, $(dtb-y)) +obj-$(CONFIG_MACH_PISTACHIO) += pistachio_marduk.dtb.o # Force kbuild to make empty built-in.o if necessary obj- += dummy.o -- cgit v1.2.1 From 6e62a888029b4adbbc55894eaa8b929221113948 Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Sat, 17 Jun 2017 13:52:49 -0700 Subject: MIPS: generic: Support MIPS Boston development boards Add support for the MIPS Boston development board to generic kernels, which essentially amounts to: - Adding the device tree source for the MIPS Boston board. - Adding a Kconfig fragment which enables the appropriate drivers for the MIPS Boston board. With these changes in place generic kernels will support the board by default, and kernels with only the drivers needed for Boston enabled can be configured by setting BOARDS=boston during configuration. For example: $ make ARCH=mips 64r6el_defconfig BOARDS=boston Signed-off-by: Paul Burton Reviewed-by: James Hogan Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/16485/ Signed-off-by: Ralf Baechle --- arch/mips/boot/dts/img/Makefile | 2 + arch/mips/boot/dts/img/boston.dts | 224 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 226 insertions(+) create mode 100644 arch/mips/boot/dts/img/boston.dts (limited to 'arch/mips/boot/dts') diff --git a/arch/mips/boot/dts/img/Makefile b/arch/mips/boot/dts/img/Makefile index c178cf56f5b8..3d70958d0f5a 100644 --- a/arch/mips/boot/dts/img/Makefile +++ b/arch/mips/boot/dts/img/Makefile @@ -1,3 +1,5 @@ +dtb-$(CONFIG_FIT_IMAGE_FDT_BOSTON) += boston.dtb + dtb-$(CONFIG_MACH_PISTACHIO) += pistachio_marduk.dtb obj-$(CONFIG_MACH_PISTACHIO) += pistachio_marduk.dtb.o diff --git a/arch/mips/boot/dts/img/boston.dts b/arch/mips/boot/dts/img/boston.dts new file mode 100644 index 000000000000..53bfa29a7093 --- /dev/null +++ b/arch/mips/boot/dts/img/boston.dts @@ -0,0 +1,224 @@ +/dts-v1/; + +#include +#include +#include +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "img,boston"; + + chosen { + stdout-path = "uart0:115200"; + }; + + aliases { + uart0 = &uart0; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "img,mips"; + reg = <0>; + clocks = <&clk_boston BOSTON_CLK_CPU>; + }; + }; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x10000000>; + }; + + pci0: pci@10000000 { + compatible = "xlnx,axi-pcie-host-1.00.a"; + device_type = "pci"; + reg = <0x10000000 0x2000000>; + + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + + interrupt-parent = <&gic>; + interrupts = ; + + ranges = <0x02000000 0 0x40000000 + 0x40000000 0 0x40000000>; + + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pci0_intc 1>, + <0 0 0 2 &pci0_intc 2>, + <0 0 0 3 &pci0_intc 3>, + <0 0 0 4 &pci0_intc 4>; + + pci0_intc: interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + }; + + pci1: pci@12000000 { + compatible = "xlnx,axi-pcie-host-1.00.a"; + device_type = "pci"; + reg = <0x12000000 0x2000000>; + + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + + interrupt-parent = <&gic>; + interrupts = ; + + ranges = <0x02000000 0 0x20000000 + 0x20000000 0 0x20000000>; + + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pci1_intc 1>, + <0 0 0 2 &pci1_intc 2>, + <0 0 0 3 &pci1_intc 3>, + <0 0 0 4 &pci1_intc 4>; + + pci1_intc: interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + }; + + pci2: pci@14000000 { + compatible = "xlnx,axi-pcie-host-1.00.a"; + device_type = "pci"; + reg = <0x14000000 0x2000000>; + + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + + interrupt-parent = <&gic>; + interrupts = ; + + ranges = <0x02000000 0 0x16000000 + 0x16000000 0 0x100000>; + + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pci2_intc 1>, + <0 0 0 2 &pci2_intc 2>, + <0 0 0 3 &pci2_intc 3>, + <0 0 0 4 &pci2_intc 4>; + + pci2_intc: interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + + pci2_root@0,0,0 { + compatible = "pci10ee,7021"; + reg = <0x00000000 0 0 0 0>; + + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + + eg20t_bridge@1,0,0 { + compatible = "pci8086,8800"; + reg = <0x00010000 0 0 0 0>; + + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + + eg20t_mac@2,0,1 { + compatible = "pci8086,8802"; + reg = <0x00020100 0 0 0 0>; + phy-reset-gpios = <&eg20t_gpio 6 + GPIO_ACTIVE_LOW>; + }; + + eg20t_gpio: eg20t_gpio@2,0,2 { + compatible = "pci8086,8803"; + reg = <0x00020200 0 0 0 0>; + + gpio-controller; + #gpio-cells = <2>; + }; + + eg20t_i2c@2,12,2 { + compatible = "pci8086,8817"; + reg = <0x00026200 0 0 0 0>; + + #address-cells = <1>; + #size-cells = <0>; + + rtc@0x68 { + compatible = "st,m41t81s"; + reg = <0x68>; + }; + }; + }; + }; + }; + + gic: interrupt-controller@16120000 { + compatible = "mti,gic"; + reg = <0x16120000 0x20000>; + + interrupt-controller; + #interrupt-cells = <3>; + + timer { + compatible = "mti,gic-timer"; + interrupts = ; + clocks = <&clk_boston BOSTON_CLK_CPU>; + }; + }; + + cdmm@16140000 { + compatible = "mti,mips-cdmm"; + reg = <0x16140000 0x8000>; + }; + + cpc@16200000 { + compatible = "mti,mips-cpc"; + reg = <0x16200000 0x8000>; + }; + + plat_regs: system-controller@17ffd000 { + compatible = "img,boston-platform-regs", "syscon"; + reg = <0x17ffd000 0x1000>; + + clk_boston: clock { + compatible = "img,boston-clock"; + #clock-cells = <1>; + }; + }; + + reboot: syscon-reboot { + compatible = "syscon-reboot"; + regmap = <&plat_regs>; + offset = <0x10>; + mask = <0x10>; + }; + + uart0: uart@17ffe000 { + compatible = "ns16550a"; + reg = <0x17ffe000 0x1000>; + reg-shift = <2>; + + interrupt-parent = <&gic>; + interrupts = ; + + clocks = <&clk_boston BOSTON_CLK_SYS>; + }; + + lcd: lcd@17fff000 { + compatible = "img,boston-lcd"; + reg = <0x17fff000 0x8>; + }; +}; -- cgit v1.2.1