From 6c9da387c8d5c5254857d2782bd6c314226f4f27 Mon Sep 17 00:00:00 2001 From: Jiancheng Xue Date: Sat, 23 Apr 2016 15:40:30 +0800 Subject: clk: hisilicon: add CRG driver for hi3519 soc The CRG(Clock and Reset Generator) block provides clock and reset signals for other modules in hi3519 soc. Signed-off-by: Jiancheng Xue Acked-by: Rob Herring Signed-off-by: Stephen Boyd --- drivers/clk/hisilicon/Makefile | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/clk/hisilicon/Makefile') diff --git a/drivers/clk/hisilicon/Makefile b/drivers/clk/hisilicon/Makefile index c03775350e63..e169ec7da023 100644 --- a/drivers/clk/hisilicon/Makefile +++ b/drivers/clk/hisilicon/Makefile @@ -7,6 +7,7 @@ obj-y += clk.o clkgate-separated.o clkdivider-hi6220.o obj-$(CONFIG_ARCH_HI3xxx) += clk-hi3620.o obj-$(CONFIG_ARCH_HIP04) += clk-hip04.o obj-$(CONFIG_ARCH_HIX5HD2) += clk-hix5hd2.o +obj-$(CONFIG_COMMON_CLK_HI3519) += clk-hi3519.o obj-$(CONFIG_COMMON_CLK_HI6220) += clk-hi6220.o obj-$(CONFIG_RESET_HISI) += reset.o obj-$(CONFIG_STUB_CLK_HI6220) += clk-hi6220-stub.o -- cgit v1.2.1