From a08082f8e4e1c292df174a9ed303cfbff2fbe2cb Mon Sep 17 00:00:00 2001 From: Gustavo Romero Date: Sun, 31 Dec 2017 18:20:46 -0500 Subject: powerpc/selftests: Check endianness on trap in TM Add a selftest to check if endianness is flipped inadvertently to BE (MSR.LE set to zero) on BE and LE machines when a trap is caught in transactional mode and load_fp and load_vec are zero, i.e. when MSR.FP and MSR.VEC are zeroed (disabled). Signed-off-by: Gustavo Romero Signed-off-by: Michael Ellerman --- tools/testing/selftests/powerpc/tm/.gitignore | 1 + 1 file changed, 1 insertion(+) (limited to 'tools/testing/selftests/powerpc/tm/.gitignore') diff --git a/tools/testing/selftests/powerpc/tm/.gitignore b/tools/testing/selftests/powerpc/tm/.gitignore index 241a4a4ee0e4..bb90d4b79524 100644 --- a/tools/testing/selftests/powerpc/tm/.gitignore +++ b/tools/testing/selftests/powerpc/tm/.gitignore @@ -13,3 +13,4 @@ tm-signal-context-chk-vmx tm-signal-context-chk-vsx tm-vmx-unavail tm-unavailable +tm-trap -- cgit v1.2.1