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| author | Gabriel Fernandez <gabriel.fernandez@linaro.org> | 2015-06-23 16:09:00 +0200 |
|---|---|---|
| committer | Maxime Coquelin <maxime.coquelin@st.com> | 2015-07-22 11:41:33 +0200 |
| commit | 5eb26c60590983e11f567916a83d1f0a70986553 (patch) | |
| tree | 4c3073dc88c4bfc9fcf1982cee21513ca636fbc0 /arch/arm/boot/dts/stih407-clock.dtsi | |
| parent | 0a8c739c066254195b86bc8387fe16e5f72a5bdd (diff) | |
| download | linux-rt-5eb26c60590983e11f567916a83d1f0a70986553.tar.gz | |
ARM: STi: DT: Rename st_pll3200c32_407_c0_x into st_pll3200c32_cx_x
Use a generic name for this kind of PLL
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
Diffstat (limited to 'arch/arm/boot/dts/stih407-clock.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/stih407-clock.dtsi | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/boot/dts/stih407-clock.dtsi b/arch/arm/boot/dts/stih407-clock.dtsi index e65744fc12ab..ad45f5e8fac7 100644 --- a/arch/arm/boot/dts/stih407-clock.dtsi +++ b/arch/arm/boot/dts/stih407-clock.dtsi @@ -134,7 +134,7 @@ clk_s_c0_pll0: clk-s-c0-pll0 { #clock-cells = <1>; - compatible = "st,stih407-plls-c32-c0_0", "st,clkgen-plls-c32"; + compatible = "st,plls-c32-cx_0", "st,clkgen-plls-c32"; clocks = <&clk_sysin>; @@ -143,7 +143,7 @@ clk_s_c0_pll1: clk-s-c0-pll1 { #clock-cells = <1>; - compatible = "st,stih407-plls-c32-c0_1", "st,clkgen-plls-c32"; + compatible = "st,plls-c32-cx_1", "st,clkgen-plls-c32"; clocks = <&clk_sysin>; |