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| author | Maxime Ripard <maxime.ripard@free-electrons.com> | 2013-02-04 23:32:39 +0100 |
|---|---|---|
| committer | Olof Johansson <olof@lixom.net> | 2013-02-05 11:02:39 -0800 |
| commit | b60decad7791694a36ad218cede77a407c1475ce (patch) | |
| tree | 7631316bb6a52551f556dfeb5fd4880ddd099340 /arch/arm/mach-sunxi | |
| parent | b28eaacfbbccef527834d48f118919b39ec8d213 (diff) | |
| download | linux-rt-b60decad7791694a36ad218cede77a407c1475ce.tar.gz | |
sunxi: Cleanup the reset code and add meaningful registers defines
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat (limited to 'arch/arm/mach-sunxi')
| -rw-r--r-- | arch/arm/mach-sunxi/sunxi.c | 19 |
1 files changed, 15 insertions, 4 deletions
diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c index fb8fbcecb17f..23afb732cb40 100644 --- a/arch/arm/mach-sunxi/sunxi.c +++ b/arch/arm/mach-sunxi/sunxi.c @@ -27,7 +27,10 @@ #include "sunxi.h" #define WATCHDOG_CTRL_REG 0x00 +#define WATCHDOG_CTRL_RESTART (1 << 0) #define WATCHDOG_MODE_REG 0x04 +#define WATCHDOG_MODE_ENABLE (1 << 0) +#define WATCHDOG_MODE_RESET_ENABLE (1 << 1) static void __iomem *wdt_base; @@ -48,11 +51,19 @@ static void sunxi_restart(char mode, const char *cmd) return; /* Enable timer and set reset bit in the watchdog */ - writel(3, wdt_base + WATCHDOG_MODE_REG); - writel(0xa57 << 1 | 1, wdt_base + WATCHDOG_CTRL_REG); - while(1) { + writel(WATCHDOG_MODE_ENABLE | WATCHDOG_MODE_RESET_ENABLE, + wdt_base + WATCHDOG_MODE_REG); + + /* + * Restart the watchdog. The default (and lowest) interval + * value for the watchdog is 0.5s. + */ + writel(WATCHDOG_CTRL_RESTART, wdt_base + WATCHDOG_CTRL_REG); + + while (1) { mdelay(5); - writel(3, wdt_base + WATCHDOG_MODE_REG); + writel(WATCHDOG_MODE_ENABLE | WATCHDOG_MODE_RESET_ENABLE, + wdt_base + WATCHDOG_MODE_REG); } } |