diff options
| author | Ben Dooks <ben-linux@fluff.org> | 2008-12-18 16:17:37 +0000 |
|---|---|---|
| committer | Ben Dooks <ben-linux@fluff.org> | 2008-12-18 16:17:37 +0000 |
| commit | 56c035c9ce1f1850969778af6a4cc0b99089b6c8 (patch) | |
| tree | b6f1998be0c1e6bb623a0c55e8ba04d74bb58cf2 /arch/arm/plat-s3c64xx/include/plat/gpio-bank-e.h | |
| parent | 7f2754378f3522a42daafdbb9d2385f341008454 (diff) | |
| parent | 438a5d42e052ec6126c5f1e24763b711210db33e (diff) | |
| download | linux-rt-56c035c9ce1f1850969778af6a4cc0b99089b6c8.tar.gz | |
Merge branch 'next-s3c64xx-device' into next-merged
Conflicts:
arch/arm/mach-s3c2440/mach-at2440evb.c
Diffstat (limited to 'arch/arm/plat-s3c64xx/include/plat/gpio-bank-e.h')
| -rw-r--r-- | arch/arm/plat-s3c64xx/include/plat/gpio-bank-e.h | 44 |
1 files changed, 44 insertions, 0 deletions
diff --git a/arch/arm/plat-s3c64xx/include/plat/gpio-bank-e.h b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-e.h new file mode 100644 index 000000000000..7fcf3d8e0a48 --- /dev/null +++ b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-e.h @@ -0,0 +1,44 @@ +/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-e.h + * + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * http://armlinux.simtec.co.uk/ + * + * GPIO Bank E register and configuration definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#define S3C64XX_GPECON (S3C64XX_GPE_BASE + 0x00) +#define S3C64XX_GPEDAT (S3C64XX_GPE_BASE + 0x04) +#define S3C64XX_GPEPUD (S3C64XX_GPE_BASE + 0x08) +#define S3C64XX_GPECONSLP (S3C64XX_GPE_BASE + 0x0c) +#define S3C64XX_GPEPUDSLP (S3C64XX_GPE_BASE + 0x10) + +#define S3C64XX_GPE_CONMASK(__gpio) (0xf << ((__gpio) * 4)) +#define S3C64XX_GPE_INPUT(__gpio) (0x0 << ((__gpio) * 4)) +#define S3C64XX_GPE_OUTPUT(__gpio) (0x1 << ((__gpio) * 4)) + +#define S3C64XX_GPE0_PCM1_SCLK (0x02 << 0) +#define S3C64XX_GPE0_I2S1_CLK (0x03 << 0) +#define S3C64XX_GPE0_AC97_BITCLK (0x04 << 0) + +#define S3C64XX_GPE1_PCM1_EXTCLK (0x02 << 4) +#define S3C64XX_GPE1_I2S1_CDCLK (0x03 << 4) +#define S3C64XX_GPE1_AC97_nRESET (0x04 << 4) + +#define S3C64XX_GPE2_PCM1_FSYNC (0x02 << 8) +#define S3C64XX_GPE2_I2S1_LRCLK (0x03 << 8) +#define S3C64XX_GPE2_AC97_SYNC (0x04 << 8) + +#define S3C64XX_GPE3_PCM1_SIN (0x02 << 12) +#define S3C64XX_GPE3_I2S1_DI (0x03 << 12) +#define S3C64XX_GPE3_AC97_SDI (0x04 << 12) + +#define S3C64XX_GPE4_PCM1_SOUT (0x02 << 16) +#define S3C64XX_GPE4_I2S1_D0 (0x03 << 16) +#define S3C64XX_GPE4_AC97_SDO (0x04 << 16) + |