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| author | Matt Redfearn <matt.redfearn@imgtec.com> | 2016-09-20 09:47:25 +0100 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2016-10-05 01:31:20 +0200 |
| commit | e710d6668309d227cc7a46e9c222d97d4a502b9e (patch) | |
| tree | e23ef0deba73c43be007abbcbc4444c4dfa1a2e7 /arch/mips/mm | |
| parent | b2ff71718e6025fed33a693a1772e2ed39f25d6c (diff) | |
| download | linux-rt-e710d6668309d227cc7a46e9c222d97d4a502b9e.tar.gz | |
MIPS: tlb-r4k: If there are wired entries, don't use TLBINVF
When adding a wired entry to the TLB via add_wired_entry, the tlb is
flushed with local_flush_tlb_all, which on CPUs with TLBINV results in
the new wired entry being flushed again.
Behavior of the TLBINV instruction applies to all applicable TLB entries
and is unaffected by the setting of the Wired register. Therefore if
the TLB has any wired entries, fall back to iterating over the entries
rather than blasting them all using TLBINVF.
Signed-off-by: Matt Redfearn <matt.redfearn@imgtec.com>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Ohad Ben-Cohen <ohad@wizery.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: lisa.parratt@imgtec.com
Cc: Hugh Dickins <hughd@google.com>
Cc: Huacai Chen <chenhc@lemote.com>
Cc: David S. Miller <davem@davemloft.net>
Cc: James Hogan <james.hogan@imgtec.com>
Cc: Paul Burton <paul.burton@imgtec.com>
Cc: Andrew Morton <akpm@linux-foundation.org>
Cc: linux-mips@linux-mips.org
Cc: linux-remoteproc@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/14283/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/mm')
| -rw-r--r-- | arch/mips/mm/tlb-r4k.c | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/arch/mips/mm/tlb-r4k.c b/arch/mips/mm/tlb-r4k.c index e8b335c16295..4953c1a8cdfd 100644 --- a/arch/mips/mm/tlb-r4k.c +++ b/arch/mips/mm/tlb-r4k.c @@ -67,8 +67,11 @@ void local_flush_tlb_all(void) entry = read_c0_wired(); - /* Blast 'em all away. */ - if (cpu_has_tlbinv) { + /* + * Blast 'em all away. + * If there are any wired entries, fall back to iterating + */ + if (cpu_has_tlbinv && !entry) { if (current_cpu_data.tlbsizevtlb) { write_c0_index(0); mtc0_tlbw_hazard(); |