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| author | Alex Deucher <alexander.deucher@amd.com> | 2013-06-26 00:35:16 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2013-06-27 19:15:47 -0400 |
| commit | f85392bcf94c5ae8bf55852827dcfa46f86502dc (patch) | |
| tree | 3d1b8cbcc56df441394d668c1f731e803fbcfbd2 /drivers/gpu/drm/radeon/cypress_dpm.c | |
| parent | 7c464f68b361aa05f964e22f7a8be4e7a7698a70 (diff) | |
| download | linux-rt-f85392bcf94c5ae8bf55852827dcfa46f86502dc.tar.gz | |
drm/radeon: add dpm UVD handling for evergreen/btc asics
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/cypress_dpm.c')
| -rw-r--r-- | drivers/gpu/drm/radeon/cypress_dpm.c | 10 |
1 files changed, 9 insertions, 1 deletions
diff --git a/drivers/gpu/drm/radeon/cypress_dpm.c b/drivers/gpu/drm/radeon/cypress_dpm.c index 91434acfe4b8..ce7961935a88 100644 --- a/drivers/gpu/drm/radeon/cypress_dpm.c +++ b/drivers/gpu/drm/radeon/cypress_dpm.c @@ -690,7 +690,8 @@ int cypress_convert_power_level_to_smc(struct radeon_device *rdev, level->mcFlags = 0; if (pi->mclk_stutter_mode_threshold && - (pl->mclk <= pi->mclk_stutter_mode_threshold)) { + (pl->mclk <= pi->mclk_stutter_mode_threshold) && + !eg_pi->uvd_enabled) { level->mcFlags |= SMC_MC_STUTTER_EN; if (eg_pi->sclk_deep_sleep) level->stateFlags |= PPSMC_STATEFLAG_AUTO_PULSE_SKIP; @@ -1938,6 +1939,7 @@ int cypress_dpm_set_power_state(struct radeon_device *rdev) if (eg_pi->pcie_performance_request) cypress_notify_link_speed_change_before_state_change(rdev); + rv770_set_uvd_clock_before_set_eng_clock(rdev); rv770_halt_smc(rdev); cypress_upload_sw_state(rdev); @@ -1948,6 +1950,7 @@ int cypress_dpm_set_power_state(struct radeon_device *rdev) rv770_resume_smc(rdev); rv770_set_sw_state(rdev); + rv770_set_uvd_clock_after_set_eng_clock(rdev); if (eg_pi->pcie_performance_request) cypress_notify_link_speed_change_after_state_change(rdev); @@ -2012,6 +2015,11 @@ int cypress_dpm_init(struct radeon_device *rdev) pi->mclk_edc_enable_threshold = 40000; eg_pi->mclk_edc_wr_enable_threshold = 40000; + pi->rlp = RV770_RLP_DFLT; + pi->rmp = RV770_RMP_DFLT; + pi->lhp = RV770_LHP_DFLT; + pi->lmp = RV770_LMP_DFLT; + pi->voltage_control = radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC); |