diff options
Diffstat (limited to 'arch/m68knommu/platform/5307')
| -rw-r--r-- | arch/m68knommu/platform/5307/Makefile | 1 | ||||
| -rw-r--r-- | arch/m68knommu/platform/5307/entry.S | 46 | ||||
| -rw-r--r-- | arch/m68knommu/platform/5307/head.S | 82 | ||||
| -rw-r--r-- | arch/m68knommu/platform/5307/pit.c | 37 | ||||
| -rw-r--r-- | arch/m68knommu/platform/5307/timers.c | 49 |
5 files changed, 74 insertions, 141 deletions
diff --git a/arch/m68knommu/platform/5307/Makefile b/arch/m68knommu/platform/5307/Makefile index 8d1619dc1ea6..2fd37dcc309b 100644 --- a/arch/m68knommu/platform/5307/Makefile +++ b/arch/m68knommu/platform/5307/Makefile @@ -25,6 +25,7 @@ obj-$(CONFIG_M5249) += timers.o obj-$(CONFIG_M527x) += pit.o obj-$(CONFIG_M5272) += timers.o obj-$(CONFIG_M5307) += config.o timers.o +obj-$(CONFIG_M532x) += timers.o obj-$(CONFIG_M528x) += pit.o obj-$(CONFIG_M5407) += timers.o diff --git a/arch/m68knommu/platform/5307/entry.S b/arch/m68knommu/platform/5307/entry.S index 89b180d4ed6a..9ddf5476ef8f 100644 --- a/arch/m68knommu/platform/5307/entry.S +++ b/arch/m68knommu/platform/5307/entry.S @@ -4,8 +4,8 @@ * Copyright (C) 1999-2002, Greg Ungerer (gerg@snapgear.com) * Copyright (C) 1998 D. Jeff Dionne <jeff@lineo.ca>, * Kenneth Albanowski <kjahds@kjahds.com>, - * Copyright (C) 2000 Lineo Inc. (www.lineo.com) - * Copyright (C) 2004 Macq Electronique SA. (www.macqel.com) + * Copyright (C) 2000 Lineo Inc. (www.lineo.com) + * Copyright (C) 2004-2006 Macq Electronique SA. (www.macqel.com) * * Based on: * @@ -56,32 +56,27 @@ sw_usp: .globl inthandler .globl fasthandler +enosys: + mov.l #sys_ni_syscall,%d3 + bra 1f + ENTRY(system_call) SAVE_ALL move #0x2000,%sr /* enable intrs again */ - movel #-LENOSYS,%d2 - movel %d2,PT_D0(%sp) /* default return value in d0 */ - /* original D0 is in orig_d0 */ - movel %d0,%d2 - - /* save top of frame */ - pea %sp@ - jbsr set_esp0 - addql #4,%sp - - cmpl #NR_syscalls,%d2 - jcc ret_from_exception + cmpl #NR_syscalls,%d0 + jcc enosys lea sys_call_table,%a0 - lsll #2,%d2 /* movel %a0@(%d2:l:4),%d3 */ - movel %a0@(%d2),%d3 - jeq ret_from_exception - lsrl #2,%d2 + lsll #2,%d0 /* movel %a0@(%d0:l:4),%d3 */ + movel %a0@(%d0),%d3 + jeq enosys +1: movel %sp,%d2 /* get thread_info pointer */ andl #-THREAD_SIZE,%d2 /* at start of kernel stack */ movel %d2,%a0 - btst #TIF_SYSCALL_TRACE,%a0@(TI_FLAGS) + movel %sp,%a0@(THREAD_ESP0) /* save top of frame */ + btst #(TIF_SYSCALL_TRACE%8),%a0@(TI_FLAGS+(31-TIF_SYSCALL_TRACE)/8) bnes 1f movel %d3,%a0 @@ -126,8 +121,8 @@ Luser_return: jne Lwork_to_do /* still work to do */ Lreturn: - move #0x2700,%sr /* disable intrs */ - movel sw_usp,%a0 /* get usp */ + move #0x2700,%sr /* disable intrs */ + movel sw_usp,%a0 /* get usp */ movel %sp@(PT_PC),%a0@- /* copy exception program counter */ movel %sp@(PT_FORMATVEC),%a0@-/* copy exception format/vector/sr */ moveml %sp@,%d1-%d5/%a0-%a2 @@ -170,7 +165,7 @@ ENTRY(inthandler) movel %d0,%sp@(PT_ORIG_D0) addql #1,local_irq_count - movew %sp@(PT_FORMATVEC),%d0 /* put exception # in d0 */ + movew %sp@(PT_FORMATVEC),%d0 /* put exception # in d0 */ andl #0x03fc,%d0 /* mask out vector only */ leal per_cpu__kstat+STAT_IRQ,%a0 @@ -184,7 +179,7 @@ ENTRY(inthandler) movel %sp,%sp@- /* push regs arg onto stack */ movel %a0@(8),%sp@- /* push devid arg */ - movel %d0,%sp@- /* push vector # on stack */ + movel %d0,%sp@- /* push vector # on stack */ movel %a0@,%a0 /* get function to call */ jbsr %a0@ /* call vector handler */ @@ -201,7 +196,7 @@ ENTRY(inthandler) ENTRY(fasthandler) SAVE_LOCAL - movew %sp@(PT_FORMATVEC),%d0 + movew %sp@(PT_FORMATVEC),%d0 andl #0x03fc,%d0 /* mask out vector only */ leal per_cpu__kstat+STAT_IRQ,%a0 @@ -210,7 +205,7 @@ ENTRY(fasthandler) movel %sp,%sp@- /* push regs arg onto stack */ clrl %sp@- /* push devid arg */ lsrl #2,%d0 /* calculate real vector # */ - movel %d0,%sp@- /* push vector # on stack */ + movel %d0,%sp@- /* push vector # on stack */ lsll #4,%d0 /* adjust for array offset */ lea irq_list,%a0 @@ -265,4 +260,3 @@ ENTRY(resume) movew %a1@(TASK_THREAD+THREAD_SR),%d0 /* restore thread status reg */ movew %d0, %sr rts - diff --git a/arch/m68knommu/platform/5307/head.S b/arch/m68knommu/platform/5307/head.S index c30c462b99b1..1d9eb301d7ac 100644 --- a/arch/m68knommu/platform/5307/head.S +++ b/arch/m68knommu/platform/5307/head.S @@ -3,7 +3,7 @@ /* * head.S -- common startup code for ColdFire CPUs. * - * (C) Copyright 1999-2004, Greg Ungerer (gerg@snapgear.com). + * (C) Copyright 1999-2006, Greg Ungerer <gerg@snapgear.com>. */ /*****************************************************************************/ @@ -19,47 +19,15 @@ /*****************************************************************************/ /* - * Define fixed memory sizes. Configuration of a fixed memory size - * overrides everything else. If the user defined a size we just - * blindly use it (they know what they are doing right :-) - */ -#if defined(CONFIG_RAM32MB) -#define MEM_SIZE 0x02000000 /* memory size 32Mb */ -#elif defined(CONFIG_RAM16MB) -#define MEM_SIZE 0x01000000 /* memory size 16Mb */ -#elif defined(CONFIG_RAM8MB) -#define MEM_SIZE 0x00800000 /* memory size 8Mb */ -#elif defined(CONFIG_RAM4MB) -#define MEM_SIZE 0x00400000 /* memory size 4Mb */ -#elif defined(CONFIG_RAM1MB) -#define MEM_SIZE 0x00100000 /* memory size 1Mb */ -#endif - -/* - * Memory size exceptions for special cases. Some boards may be set - * for auto memory sizing, but we can't do it that way for some reason. - * For example the 5206eLITE board has static RAM, and auto-detecting - * the SDRAM will do you no good at all. Same goes for the MOD5272. - */ -#ifdef CONFIG_RAMAUTO -#if defined(CONFIG_M5206eLITE) -#define MEM_SIZE 0x00100000 /* 1MiB default memory */ -#endif -#if defined(CONFIG_MOD5272) -#define MEM_SIZE 0x00800000 /* 8MiB default memory */ -#endif -#endif /* CONFIG_RAMAUTO */ - - -/* - * If we don't have a fixed memory size now, then lets build in code + * If we don't have a fixed memory size, then lets build in code * to auto detect the DRAM size. Obviously this is the prefered - * method, and should work for most boards (it won't work for those - * that do not have their RAM starting at address 0). + * method, and should work for most boards. It won't work for those + * that do not have their RAM starting at address 0, and it only + * works on SDRAM (not boards fitted with SRAM). */ -#if defined(MEM_SIZE) +#if CONFIG_RAMSIZE != 0 .macro GET_MEM_SIZE - movel #MEM_SIZE,%d0 /* hard coded memory size */ + movel #CONFIG_RAMSIZE,%d0 /* hard coded memory size */ .endm #elif defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \ @@ -98,37 +66,7 @@ .endm #else -#error "ERROR: I don't know how to determine your boards memory size?" -#endif - - -/* - * Most ColdFire boards have their DRAM starting at address 0. - * Notable exception is the 5206eLITE board, another is the MOD5272. - */ -#if defined(CONFIG_M5206eLITE) -#define MEM_BASE 0x30000000 -#endif -#if defined(CONFIG_MOD5272) -#define MEM_BASE 0x02000000 -#define VBR_BASE 0x20000000 /* vectors in SRAM */ -#endif -#if defined(CONFIG_M5208EVB) -#define MEM_BASE 0x40000000 -#endif - -#ifndef MEM_BASE -#define MEM_BASE 0x00000000 /* memory base at address 0 */ -#endif - -/* - * The default location for the vectors is at the base of RAM. - * Some boards might like to use internal SRAM or something like - * that. If no board specific header defines an alternative then - * use the base of RAM. - */ -#ifndef VBR_BASE -#define VBR_BASE MEM_BASE /* vector address */ +#error "ERROR: I don't know how to probe your boards memory size?" #endif /*****************************************************************************/ @@ -191,11 +129,11 @@ _start: * Create basic memory configuration. Set VBR accordingly, * and size memory. */ - movel #VBR_BASE,%a7 + movel #CONFIG_VECTORBASE,%a7 movec %a7,%VBR /* set vectors addr */ movel %a7,_ramvec - movel #MEM_BASE,%a7 /* mark the base of RAM */ + movel #CONFIG_RAMBASE,%a7 /* mark the base of RAM */ movel %a7,_rambase GET_MEM_SIZE /* macro code determines size */ diff --git a/arch/m68knommu/platform/5307/pit.c b/arch/m68knommu/platform/5307/pit.c index 323f2677e49d..ef174748825f 100644 --- a/arch/m68knommu/platform/5307/pit.c +++ b/arch/m68knommu/platform/5307/pit.c @@ -1,11 +1,11 @@ /***************************************************************************/ /* - * pit.c -- Motorola ColdFire PIT timer. Currently this type of - * hardware timer only exists in the Motorola ColdFire + * pit.c -- Freescale ColdFire PIT timer. Currently this type of + * hardware timer only exists in the Freescale ColdFire * 5270/5271, 5282 and other CPUs. * - * Copyright (C) 1999-2004, Greg Ungerer (gerg@snapgear.com) + * Copyright (C) 1999-2006, Greg Ungerer (gerg@snapgear.com) * Copyright (C) 2001-2004, SnapGear Inc. (www.snapgear.com) * */ @@ -18,6 +18,7 @@ #include <linux/param.h> #include <linux/init.h> #include <linux/interrupt.h> +#include <asm/io.h> #include <asm/irq.h> #include <asm/coldfire.h> #include <asm/mcfpit.h> @@ -25,13 +26,20 @@ /***************************************************************************/ +/* + * By default use timer1 as the system clock timer. + */ +#define TA(a) (MCF_IPSBAR + MCFPIT_BASE1 + (a)) + +/***************************************************************************/ + void coldfire_pit_tick(void) { - volatile struct mcfpit *tp; + unsigned short pcsr; /* Reset the ColdFire timer */ - tp = (volatile struct mcfpit *) (MCF_IPSBAR + MCFPIT_BASE1); - tp->pcsr |= MCFPIT_PCSR_PIF; + pcsr = __raw_readw(TA(MCFPIT_PCSR)); + __raw_writew(pcsr | MCFPIT_PCSR_PIF, TA(MCFPIT_PCSR)); } /***************************************************************************/ @@ -40,7 +48,6 @@ void coldfire_pit_init(irqreturn_t (*handler)(int, void *, struct pt_regs *)) { volatile unsigned char *icrp; volatile unsigned long *imrp; - volatile struct mcfpit *tp; request_irq(MCFINT_VECBASE + MCFINT_PIT1, handler, SA_INTERRUPT, "ColdFire Timer", NULL); @@ -53,27 +60,23 @@ void coldfire_pit_init(irqreturn_t (*handler)(int, void *, struct pt_regs *)) *imrp &= ~MCFPIT_IMR_IBIT; /* Set up PIT timer 1 as poll clock */ - tp = (volatile struct mcfpit *) (MCF_IPSBAR + MCFPIT_BASE1); - tp->pcsr = MCFPIT_PCSR_DISABLE; - - tp->pmr = ((MCF_CLK / 2) / 64) / HZ; - tp->pcsr = MCFPIT_PCSR_EN | MCFPIT_PCSR_PIE | MCFPIT_PCSR_OVW | - MCFPIT_PCSR_RLD | MCFPIT_PCSR_CLK64; + __raw_writew(MCFPIT_PCSR_DISABLE, TA(MCFPIT_PCSR)); + __raw_writew(((MCF_CLK / 2) / 64) / HZ, TA(MCFPIT_PMR)); + __raw_writew(MCFPIT_PCSR_EN | MCFPIT_PCSR_PIE | MCFPIT_PCSR_OVW | + MCFPIT_PCSR_RLD | MCFPIT_PCSR_CLK64, TA(MCFPIT_PCSR)); } /***************************************************************************/ unsigned long coldfire_pit_offset(void) { - volatile struct mcfpit *tp; volatile unsigned long *ipr; unsigned long pmr, pcntr, offset; - tp = (volatile struct mcfpit *) (MCF_IPSBAR + MCFPIT_BASE1); ipr = (volatile unsigned long *) (MCF_IPSBAR + MCFICM_INTC0 + MCFPIT_IMR); - pmr = *(&tp->pmr); - pcntr = *(&tp->pcntr); + pmr = __raw_readw(TA(MCFPIT_PMR)); + pcntr = __raw_readw(TA(MCFPIT_PCNTR)); /* * If we are still in the first half of the upcount and a diff --git a/arch/m68knommu/platform/5307/timers.c b/arch/m68knommu/platform/5307/timers.c index ef49596aa09c..83b8b89dfa09 100644 --- a/arch/m68knommu/platform/5307/timers.c +++ b/arch/m68knommu/platform/5307/timers.c @@ -14,6 +14,7 @@ #include <linux/param.h> #include <linux/interrupt.h> #include <linux/init.h> +#include <asm/io.h> #include <asm/irq.h> #include <asm/traps.h> #include <asm/machdep.h> @@ -24,6 +25,11 @@ /***************************************************************************/ /* + * By default use timer1 as the system clock timer. + */ +#define TA(a) (MCF_MBAR + MCFTIMER_BASE1 + (a)) + +/* * Default the timer and vector to use for ColdFire. Some ColdFire * CPU's and some boards may want different. Their sub-architecture * startup code (in config.c) can change these if they want. @@ -32,8 +38,6 @@ unsigned int mcf_timervector = 29; unsigned int mcf_profilevector = 31; unsigned int mcf_timerlevel = 5; -static volatile struct mcftimer *mcf_timerp; - /* * These provide the underlying interrupt vector support. * Unfortunately it is a little different on each ColdFire. @@ -46,20 +50,17 @@ extern int mcf_timerirqpending(int timer); void coldfire_tick(void) { /* Reset the ColdFire timer */ - mcf_timerp->ter = MCFTIMER_TER_CAP | MCFTIMER_TER_REF; + __raw_writeb(MCFTIMER_TER_CAP | MCFTIMER_TER_REF, TA(MCFTIMER_TER)); } /***************************************************************************/ void coldfire_timer_init(irqreturn_t (*handler)(int, void *, struct pt_regs *)) { - /* Set up an internal TIMER as poll clock */ - mcf_timerp = (volatile struct mcftimer *) (MCF_MBAR + MCFTIMER_BASE1); - mcf_timerp->tmr = MCFTIMER_TMR_DISABLE; - - mcf_timerp->trr = (unsigned short) ((MCF_BUSCLK / 16) / HZ); - mcf_timerp->tmr = MCFTIMER_TMR_ENORI | MCFTIMER_TMR_CLK16 | - MCFTIMER_TMR_RESTART | MCFTIMER_TMR_ENABLE; + __raw_writew(MCFTIMER_TMR_DISABLE, TA(MCFTIMER_TMR)); + __raw_writew(((MCF_BUSCLK / 16) / HZ), TA(MCFTIMER_TRR)); + __raw_writew(MCFTIMER_TMR_ENORI | MCFTIMER_TMR_CLK16 | + MCFTIMER_TMR_RESTART | MCFTIMER_TMR_ENABLE, TA(MCFTIMER_TMR)); request_irq(mcf_timervector, handler, SA_INTERRUPT, "timer", NULL); mcf_settimericr(1, mcf_timerlevel); @@ -75,13 +76,8 @@ unsigned long coldfire_timer_offset(void) { unsigned long trr, tcn, offset; - /* - * The change to pointer and de-reference is to force the compiler - * to read the registers with a single 16bit access. Otherwise it - * does some crazy 8bit read combining. - */ - tcn = *(&mcf_timerp->tcn); - trr = *(&mcf_timerp->trr); + tcn = __raw_readw(TA(MCFTIMER_TCN)); + trr = __raw_readw(TA(MCFTIMER_TRR)); offset = (tcn * (1000000 / HZ)) / trr; /* Check if we just wrapped the counters and maybe missed a tick */ @@ -95,21 +91,23 @@ unsigned long coldfire_timer_offset(void) /***************************************************************************/ /* + * By default use timer2 as the profiler clock timer. + */ +#define PA(a) (MCF_MBAR + MCFTIMER_BASE2 + (a)) + +/* * Choose a reasonably fast profile timer. Make it an odd value to * try and get good coverage of kernal operations. */ #define PROFILEHZ 1013 -static volatile struct mcftimer *mcf_proftp; - /* * Use the other timer to provide high accuracy profiling info. */ - void coldfire_profile_tick(int irq, void *dummy, struct pt_regs *regs) { /* Reset ColdFire timer2 */ - mcf_proftp->ter = MCFTIMER_TER_CAP | MCFTIMER_TER_REF; + __raw_writeb(MCFTIMER_TER_CAP | MCFTIMER_TER_REF, PA(MCFTIMER_TER)); if (current->pid) profile_tick(CPU_PROFILING, regs); } @@ -121,12 +119,11 @@ void coldfire_profile_init(void) printk(KERN_INFO "PROFILE: lodging TIMER2 @ %dHz as profile timer\n", PROFILEHZ); /* Set up TIMER 2 as high speed profile clock */ - mcf_proftp = (volatile struct mcftimer *) (MCF_MBAR + MCFTIMER_BASE2); - mcf_proftp->tmr = MCFTIMER_TMR_DISABLE; + __raw_writew(MCFTIMER_TMR_DISABLE, PA(MCFTIMER_TMR)); - mcf_proftp->trr = (unsigned short) ((MCF_CLK / 16) / PROFILEHZ); - mcf_proftp->tmr = MCFTIMER_TMR_ENORI | MCFTIMER_TMR_CLK16 | - MCFTIMER_TMR_RESTART | MCFTIMER_TMR_ENABLE; + __raw_writew(((MCF_CLK / 16) / PROFILEHZ), PA(MCFTIMER_TRR)); + __raw_writew(MCFTIMER_TMR_ENORI | MCFTIMER_TMR_CLK16 | + MCFTIMER_TMR_RESTART | MCFTIMER_TMR_ENABLE, PA(MCFTIMER_TMR)); request_irq(mcf_profilevector, coldfire_profile_tick, (SA_INTERRUPT | IRQ_FLG_FAST), "profile timer", NULL); |