diff options
Diffstat (limited to 'arch/m68knommu')
| -rw-r--r-- | arch/m68knommu/Kconfig | 242 | ||||
| -rw-r--r-- | arch/m68knommu/kernel/vmlinux.lds.S | 160 | ||||
| -rw-r--r-- | arch/m68knommu/platform/5307/entry.S | 46 | ||||
| -rw-r--r-- | arch/m68knommu/platform/5307/head.S | 82 | ||||
| -rw-r--r-- | arch/m68knommu/platform/68328/head-pilot.S | 3 | ||||
| -rw-r--r-- | arch/m68knommu/platform/68328/head-ram.S | 6 |
6 files changed, 138 insertions, 401 deletions
diff --git a/arch/m68knommu/Kconfig b/arch/m68knommu/Kconfig index d3dcdc9609ee..8b6e723eb82b 100644 --- a/arch/m68knommu/Kconfig +++ b/arch/m68knommu/Kconfig @@ -119,6 +119,11 @@ config M5307 help Motorola ColdFire 5307 processor support. +config M532x + bool "MCF532x" + help + Freescale (Motorola) ColdFire 532x processor support. + config M5407 bool "MCF5407" help @@ -133,125 +138,43 @@ config M527x config COLDFIRE bool - depends on (M5206 || M5206e || M520x || M523x || M5249 || M527x || M5272 || M528x || M5307 || M5407) + depends on (M5206 || M5206e || M520x || M523x || M5249 || M527x || M5272 || M528x || M5307 || M532x || M5407) default y -choice - prompt "CPU CLOCK Frequency" - default AUTO - -config CLOCK_AUTO - bool "AUTO" - ---help--- - Define the CPU clock frequency in use. On many boards you don't - really need to know, so you can select the AUTO option. On some - boards you need to know the real clock frequency to determine other - system timing (for example baud rate dividors, etc). Some processors - have an internal PLL and you can select a frequency to run at. - You need to know a little about the internals of your processor to - set this. If in doubt choose the AUTO option. - -config CLOCK_11MHz - bool "11MHz" - help - Select a 11MHz CPU clock frequency. - -config CLOCK_16MHz - bool "16MHz" - help - Select a 16MHz CPU clock frequency. - -config CLOCK_20MHz - bool "20MHz" - help - Select a 20MHz CPU clock frequency. - -config CLOCK_24MHz - bool "24MHz" - help - Select a 24MHz CPU clock frequency. - -config CLOCK_25MHz - bool "25MHz" - help - Select a 25MHz CPU clock frequency. - -config CLOCK_33MHz - bool "33MHz" - help - Select a 33MHz CPU clock frequency. - -config CLOCK_40MHz - bool "40MHz" - help - Select a 40MHz CPU clock frequency. - -config CLOCK_45MHz - bool "45MHz" - help - Select a 45MHz CPU clock frequency. - -config CLOCK_48MHz - bool "48MHz" - help - Select a 48MHz CPU clock frequency. - -config CLOCK_50MHz - bool "50MHz" - help - Select a 50MHz CPU clock frequency. - -config CLOCK_54MHz - bool "54MHz" - help - Select a 54MHz CPU clock frequency. - -config CLOCK_60MHz - bool "60MHz" - help - Select a 60MHz CPU clock frequency. - -config CLOCK_62_5MHz - bool "62.5MHz" - help - Select a 62.5MHz CPU clock frequency. - -config CLOCK_64MHz - bool "64MHz" - help - Select a 64MHz CPU clock frequency. - -config CLOCK_66MHz - bool "66MHz" - help - Select a 66MHz CPU clock frequency. - -config CLOCK_70MHz - bool "70MHz" - help - Select a 70MHz CPU clock frequency. - -config CLOCK_100MHz - bool "100MHz" - help - Select a 100MHz CPU clock frequency. - -config CLOCK_140MHz - bool "140MHz" - help - Select a 140MHz CPU clock frequency. - -config CLOCK_150MHz - bool "150MHz" - help - Select a 150MHz CPU clock frequency. - -config CLOCK_166MHz - bool "166MHz" +config CLOCK_SET + bool "Enable setting the CPU clock frequency" + default n help - Select a 166MHz CPU clock frequency. - -endchoice + On some CPU's you do not need to know what the core CPU clock + frequency is. On these you can disable clock setting. On some + traditional 68K parts, and on all ColdFire parts you need to set + the appropriate CPU clock frequency. On these devices many of the + onboard peripherals derive their timing from the master CPU clock + frequency. + +config CLOCK_FREQ + int "Set the core clock frequency" + default "66666666" + depends on CLOCK_SET + help + Define the CPU clock frequency in use. This is the core clock + frequency, it may or may not be the same as the external clock + crystal fitted to your board. Some processors have an internal + PLL and can have their frequency programmed at run time, others + use internal dividers. In gernal the kernel won't setup a PLL + if it is fitted (there are some expections). This value will be + specific to the exact CPU that you are using. + +config CLOCK_DIV + int "Set the core/bus clock divide ratio" + default "1" + depends on CLOCK_SET + help + On many SoC style CPUs the master CPU clock is also used to drive + on-chip peripherals. The clock that is distributed to these + peripherals is sometimes a fixed ratio of the master clock + frequency. If so then set this to the divider ration of the + master clock to the peripheral clock. If not sure then select 1. config OLDMASK bool "Old mask 5307 (1H55J) silicon" @@ -377,6 +300,12 @@ config COBRA5272 help Support for the senTec COBRA5272 board. +config AVNET5282 + bool "Avnet 5282 board support" + depends on M528x + help + Support for the Avnet 5282 board. + config M5282EVB bool "Motorola M5282EVB board support" depends on M528x @@ -419,6 +348,18 @@ config SECUREEDGEMP3 help Support for the SnapGear SecureEdge/MP3 platform. +config M5329EVB + bool "Freescale (Motorola) M5329EVB board support" + depends on M532x + help + Support for the Freescale (Motorola) M5329EVB board. + +config COBRA5329 + bool "senTec COBRA5329 board support" + depends on M532x + help + Support for the senTec COBRA5329 board. + config M5407C3 bool "Motorola M5407C3 board support" depends on M5407 @@ -487,7 +428,7 @@ config ARNEWSH config FREESCALE bool default y - depends on (M5206eC3 || M5208EVB || M5235EVB || M5249C3 || M5271EVB || M5272C3 || M5275EVB || M5282EVB || M5307C3 || M5407C3) + depends on (M5206eC3 || M5208EVB || M5235EVB || M5249C3 || M5271EVB || M5272C3 || M5275EVB || M5282EVB || M5307C3 || M5329EVB || M5407C3) config HW_FEITH bool @@ -508,6 +449,11 @@ config SNEHA bool default y depends on CPU16B + +config AVNET + bool + default y + depends on (AVNET5282) config LARGE_ALLOCS bool "Allow allocating large blocks (> 1MB) of memory" @@ -526,38 +472,46 @@ config 4KSTACKS running more threads on a system and also reduces the pressure on the VM subsystem for higher order allocations. -choice - prompt "RAM size" - default AUTO - -config RAMAUTO - bool "AUTO" - ---help--- - Configure the RAM size on your platform. Many platforms can auto - detect this, on those choose the AUTO option. Otherwise set the - RAM size you intend using. +comment "RAM configuration" -config RAM4MB - bool "4MiB" +config RAMBASE + hex "Address of the base of RAM" + default "0" help - Set RAM size to be 4MiB. + Define the address that RAM starts at. On many platforms this is + 0, the base of the address space. And this is the default. Some + platforms choose to setup their RAM at other addresses within the + processor address space. -config RAM8MB - bool "8MiB" +config RAMSIZE + hex "Size of RAM (in bytes)" + default "0x400000" help - Set RAM size to be 8MiB. + Define the size of the system RAM. If you select 0 then the + kernel will try to probe the RAM size at runtime. This is not + supported on all CPU types. -config RAM16MB - bool "16MiB" +config VECTORBASE + hex "Address of the base of system vectors" + default "0" help - Set RAM size to be 16MiB. + Define the address of the the system vectors. Commonly this is + put at the start of RAM, but it doesn't have to be. On ColdFire + platforms this address is programmed into the VBR register, thus + actually setting the address to use. -config RAM32MB - bool "32MiB" +config KERNELBASE + hex "Address of the base of kernel code" + default "0x400" help - Set RAM size to be 32MiB. - -endchoice + Typically on m68k systems the kernel will not start at the base + of RAM, but usually some small offset from it. Define the start + address of the kernel here. The most common setup will have the + processor vectors at the base of RAM and then the start of the + kernel. On some platforms some RAM is reserved for boot loaders + and the kernel starts after that. The 0x400 default was based on + a system with the RAM based at address 0, and leaving enough room + for the theoretical maximum number of 256 vectors. choice prompt "RAM bus width" @@ -565,7 +519,7 @@ choice config RAMAUTOBIT bool "AUTO" - ---help--- + help Select the physical RAM data bus size. Not needed on most platforms, so you can generally choose AUTO. @@ -599,7 +553,9 @@ config RAMKERNEL config ROMKERNEL bool "ROM" help - The kernel will be resident in FLASH/ROM when running. + The kernel will be resident in FLASH/ROM when running. This is + often referred to as Execute-in-Place (XIP), since the kernel + code executes from the position it is stored in the FLASH/ROM. endchoice diff --git a/arch/m68knommu/kernel/vmlinux.lds.S b/arch/m68knommu/kernel/vmlinux.lds.S index a331cc90797c..6a2f0c693254 100644 --- a/arch/m68knommu/kernel/vmlinux.lds.S +++ b/arch/m68knommu/kernel/vmlinux.lds.S @@ -1,7 +1,7 @@ /* * vmlinux.lds.S -- master linker script for m68knommu arch * - * (C) Copyright 2002-2004, Greg Ungerer <gerg@snapgear.com> + * (C) Copyright 2002-2006, Greg Ungerer <gerg@snapgear.com> * * This ends up looking compilcated, because of the number of * address variations for ram and rom/flash layouts. The real @@ -22,13 +22,7 @@ #define ROM_START 0x10c10400 #define ROM_LENGTH 0xfec00 #define ROM_END 0x10d00000 -#define RAMVEC_START 0x00000000 -#define RAMVEC_LENGTH 0x400 -#define RAM_START 0x10000400 -#define RAM_LENGTH 0xffc00 -#define RAM_END 0x10100000 -#define _ramend _ram_end_notused -#define DATA_ADDR RAM_START +#define DATA_ADDR CONFIG_KERNELBASE #endif /* @@ -41,11 +35,6 @@ #define ROM_START 0x10c10400 #define ROM_LENGTH 0x1efc00 #define ROM_END 0x10e00000 -#define RAMVEC_START 0x00000000 -#define RAMVEC_LENGTH 0x400 -#define RAM_START 0x00020400 -#define RAM_LENGTH 0x7dfc00 -#define RAM_END 0x00800000 #endif #ifdef CONFIG_ROMKERNEL #define ROMVEC_START 0x10c10000 @@ -53,11 +42,6 @@ #define ROM_START 0x10c10400 #define ROM_LENGTH 0x1efc00 #define ROM_END 0x10e00000 -#define RAMVEC_START 0x00000000 -#define RAMVEC_LENGTH 0x400 -#define RAM_START 0x00020000 -#define RAM_LENGTH 0x600000 -#define RAM_END 0x00800000 #endif #ifdef CONFIG_HIMEMKERNEL #define ROMVEC_START 0x00600000 @@ -65,141 +49,28 @@ #define ROM_START 0x00600400 #define ROM_LENGTH 0x1efc00 #define ROM_END 0x007f0000 -#define RAMVEC_START 0x00000000 -#define RAMVEC_LENGTH 0x400 -#define RAM_START 0x00020000 -#define RAM_LENGTH 0x5e0000 -#define RAM_END 0x00600000 #endif #endif -#ifdef CONFIG_DRAGEN2 -#define RAM_START 0x10000 -#define RAM_LENGTH 0x7f0000 -#endif - #ifdef CONFIG_UCQUICC #define ROMVEC_START 0x00000000 #define ROMVEC_LENGTH 0x404 #define ROM_START 0x00000404 #define ROM_LENGTH 0x1ff6fc #define ROM_END 0x00200000 -#define RAMVEC_START 0x00200000 -#define RAMVEC_LENGTH 0x404 -#define RAM_START 0x00200404 -#define RAM_LENGTH 0x1ff6fc -#define RAM_END 0x00400000 -#endif - -/* - * The standard Arnewsh 5206 board only has 1MiB of ram. Not normally - * enough to be useful. Assume the user has fitted something larger, - * at least 4MiB in size. No point in not letting the kernel completely - * link, it will be obvious if it is too big when they go to load it. - */ -#if defined(CONFIG_ARN5206) -#define RAM_START 0x10000 -#define RAM_LENGTH 0x3f0000 -#endif - -/* - * The Motorola 5206eLITE board only has 1MiB of static RAM. - */ -#if defined(CONFIG_ELITE) -#define RAM_START 0x30020000 -#define RAM_LENGTH 0xe0000 -#endif - -/* - * All the Motorola eval boards have the same basic arrangement. - * The end of RAM will vary depending on how much ram is fitted, - * but this isn't important here, we assume at least 4MiB. - */ -#if defined(CONFIG_M5206eC3) || defined(CONFIG_M5249C3) || \ - defined(CONFIG_M5272C3) || defined(CONFIG_M5307C3) || \ - defined(CONFIG_ARN5307) || defined(CONFIG_M5407C3) || \ - defined(CONFIG_M5271EVB) || defined(CONFIG_M5275EVB) || \ - defined(CONFIG_M5235EVB) -#define RAM_START 0x20000 -#define RAM_LENGTH 0x3e0000 -#endif - -/* - * The Freescale 5208EVB board has 32MB of RAM. - */ -#if defined(CONFIG_M5208EVB) -#define RAM_START 0x40020000 -#define RAM_LENGTH 0x01fe0000 -#endif - -/* - * The senTec COBRA5272 board has nearly the same memory layout as - * the M5272C3. We assume 16MiB ram. - */ -#if defined(CONFIG_COBRA5272) -#define RAM_START 0x20000 -#define RAM_LENGTH 0xfe0000 -#endif - -#if defined(CONFIG_M5282EVB) -#define RAM_START 0x10000 -#define RAM_LENGTH 0x3f0000 -#endif - -/* - * The senTec COBRA5282 board has the same memory layout as the M5282EVB. - */ -#if defined(CONFIG_COBRA5282) -#define RAM_START 0x10000 -#define RAM_LENGTH 0x3f0000 -#endif - - -/* - * The EMAC SoM-5282EM module. - */ -#if defined(CONFIG_SOM5282EM) -#define RAM_START 0x10000 -#define RAM_LENGTH 0xff0000 -#endif - - -/* - * These flash boot boards use all of ram for operation. Again the - * actual memory size is not important here, assume at least 4MiB. - * They currently have no support for running in flash. - */ -#if defined(CONFIG_NETtel) || defined(CONFIG_eLIA) || \ - defined(CONFIG_DISKtel) || defined(CONFIG_SECUREEDGEMP3) || \ - defined(CONFIG_HW_FEITH) -#define RAM_START 0x400 -#define RAM_LENGTH 0x3ffc00 -#endif - -/* - * Sneha Boards mimimun memory - * The end of RAM will vary depending on how much ram is fitted, - * but this isn't important here, we assume at least 4MiB. - */ -#if defined(CONFIG_CPU16B) -#define RAM_START 0x20000 -#define RAM_LENGTH 0x3e0000 -#endif - -#if defined(CONFIG_MOD5272) -#define RAM_START 0x02000000 -#define RAM_LENGTH 0x00800000 -#define RAMVEC_START 0x20000000 -#define RAMVEC_LENGTH 0x00000400 #endif #if defined(CONFIG_RAMKERNEL) +#define RAM_START CONFIG_KERNELBASE +#define RAM_LENGTH (CONFIG_RAMBASE + CONFIG_RAMSIZE - CONFIG_KERNELBASE) #define TEXT ram #define DATA ram #define INIT ram #define BSS ram #endif #if defined(CONFIG_ROMKERNEL) || defined(CONFIG_HIMEMKERNEL) +#define RAM_START CONFIG_RAMBASE +#define RAM_LENGTH CONFIG_RAMSIZE #define TEXT rom #define DATA ram #define INIT ram @@ -215,13 +86,7 @@ OUTPUT_ARCH(m68k) ENTRY(_start) MEMORY { -#ifdef RAMVEC_START - ramvec : ORIGIN = RAMVEC_START, LENGTH = RAMVEC_LENGTH -#endif ram : ORIGIN = RAM_START, LENGTH = RAM_LENGTH -#ifdef RAM_END - eram : ORIGIN = RAM_END, LENGTH = 0 -#endif #ifdef ROM_START romvec : ORIGIN = ROMVEC_START, LENGTH = ROMVEC_LENGTH rom : ORIGIN = ROM_START, LENGTH = ROM_LENGTH @@ -308,12 +173,6 @@ SECTIONS { __rom_end = . ; } > erom #endif -#ifdef RAMVEC_START - . = RAMVEC_START ; - .ramvec : { - __ramvec = .; - } > ramvec -#endif .data DATA_ADDR : { . = ALIGN(4); @@ -373,12 +232,5 @@ SECTIONS { _ebss = . ; } > BSS -#ifdef RAM_END - . = RAM_END ; - .eram : { - __ramend = . ; - _ramend = . ; - } > eram -#endif } diff --git a/arch/m68knommu/platform/5307/entry.S b/arch/m68knommu/platform/5307/entry.S index 89b180d4ed6a..9ddf5476ef8f 100644 --- a/arch/m68knommu/platform/5307/entry.S +++ b/arch/m68knommu/platform/5307/entry.S @@ -4,8 +4,8 @@ * Copyright (C) 1999-2002, Greg Ungerer (gerg@snapgear.com) * Copyright (C) 1998 D. Jeff Dionne <jeff@lineo.ca>, * Kenneth Albanowski <kjahds@kjahds.com>, - * Copyright (C) 2000 Lineo Inc. (www.lineo.com) - * Copyright (C) 2004 Macq Electronique SA. (www.macqel.com) + * Copyright (C) 2000 Lineo Inc. (www.lineo.com) + * Copyright (C) 2004-2006 Macq Electronique SA. (www.macqel.com) * * Based on: * @@ -56,32 +56,27 @@ sw_usp: .globl inthandler .globl fasthandler +enosys: + mov.l #sys_ni_syscall,%d3 + bra 1f + ENTRY(system_call) SAVE_ALL move #0x2000,%sr /* enable intrs again */ - movel #-LENOSYS,%d2 - movel %d2,PT_D0(%sp) /* default return value in d0 */ - /* original D0 is in orig_d0 */ - movel %d0,%d2 - - /* save top of frame */ - pea %sp@ - jbsr set_esp0 - addql #4,%sp - - cmpl #NR_syscalls,%d2 - jcc ret_from_exception + cmpl #NR_syscalls,%d0 + jcc enosys lea sys_call_table,%a0 - lsll #2,%d2 /* movel %a0@(%d2:l:4),%d3 */ - movel %a0@(%d2),%d3 - jeq ret_from_exception - lsrl #2,%d2 + lsll #2,%d0 /* movel %a0@(%d0:l:4),%d3 */ + movel %a0@(%d0),%d3 + jeq enosys +1: movel %sp,%d2 /* get thread_info pointer */ andl #-THREAD_SIZE,%d2 /* at start of kernel stack */ movel %d2,%a0 - btst #TIF_SYSCALL_TRACE,%a0@(TI_FLAGS) + movel %sp,%a0@(THREAD_ESP0) /* save top of frame */ + btst #(TIF_SYSCALL_TRACE%8),%a0@(TI_FLAGS+(31-TIF_SYSCALL_TRACE)/8) bnes 1f movel %d3,%a0 @@ -126,8 +121,8 @@ Luser_return: jne Lwork_to_do /* still work to do */ Lreturn: - move #0x2700,%sr /* disable intrs */ - movel sw_usp,%a0 /* get usp */ + move #0x2700,%sr /* disable intrs */ + movel sw_usp,%a0 /* get usp */ movel %sp@(PT_PC),%a0@- /* copy exception program counter */ movel %sp@(PT_FORMATVEC),%a0@-/* copy exception format/vector/sr */ moveml %sp@,%d1-%d5/%a0-%a2 @@ -170,7 +165,7 @@ ENTRY(inthandler) movel %d0,%sp@(PT_ORIG_D0) addql #1,local_irq_count - movew %sp@(PT_FORMATVEC),%d0 /* put exception # in d0 */ + movew %sp@(PT_FORMATVEC),%d0 /* put exception # in d0 */ andl #0x03fc,%d0 /* mask out vector only */ leal per_cpu__kstat+STAT_IRQ,%a0 @@ -184,7 +179,7 @@ ENTRY(inthandler) movel %sp,%sp@- /* push regs arg onto stack */ movel %a0@(8),%sp@- /* push devid arg */ - movel %d0,%sp@- /* push vector # on stack */ + movel %d0,%sp@- /* push vector # on stack */ movel %a0@,%a0 /* get function to call */ jbsr %a0@ /* call vector handler */ @@ -201,7 +196,7 @@ ENTRY(inthandler) ENTRY(fasthandler) SAVE_LOCAL - movew %sp@(PT_FORMATVEC),%d0 + movew %sp@(PT_FORMATVEC),%d0 andl #0x03fc,%d0 /* mask out vector only */ leal per_cpu__kstat+STAT_IRQ,%a0 @@ -210,7 +205,7 @@ ENTRY(fasthandler) movel %sp,%sp@- /* push regs arg onto stack */ clrl %sp@- /* push devid arg */ lsrl #2,%d0 /* calculate real vector # */ - movel %d0,%sp@- /* push vector # on stack */ + movel %d0,%sp@- /* push vector # on stack */ lsll #4,%d0 /* adjust for array offset */ lea irq_list,%a0 @@ -265,4 +260,3 @@ ENTRY(resume) movew %a1@(TASK_THREAD+THREAD_SR),%d0 /* restore thread status reg */ movew %d0, %sr rts - diff --git a/arch/m68knommu/platform/5307/head.S b/arch/m68knommu/platform/5307/head.S index c30c462b99b1..1d9eb301d7ac 100644 --- a/arch/m68knommu/platform/5307/head.S +++ b/arch/m68knommu/platform/5307/head.S @@ -3,7 +3,7 @@ /* * head.S -- common startup code for ColdFire CPUs. * - * (C) Copyright 1999-2004, Greg Ungerer (gerg@snapgear.com). + * (C) Copyright 1999-2006, Greg Ungerer <gerg@snapgear.com>. */ /*****************************************************************************/ @@ -19,47 +19,15 @@ /*****************************************************************************/ /* - * Define fixed memory sizes. Configuration of a fixed memory size - * overrides everything else. If the user defined a size we just - * blindly use it (they know what they are doing right :-) - */ -#if defined(CONFIG_RAM32MB) -#define MEM_SIZE 0x02000000 /* memory size 32Mb */ -#elif defined(CONFIG_RAM16MB) -#define MEM_SIZE 0x01000000 /* memory size 16Mb */ -#elif defined(CONFIG_RAM8MB) -#define MEM_SIZE 0x00800000 /* memory size 8Mb */ -#elif defined(CONFIG_RAM4MB) -#define MEM_SIZE 0x00400000 /* memory size 4Mb */ -#elif defined(CONFIG_RAM1MB) -#define MEM_SIZE 0x00100000 /* memory size 1Mb */ -#endif - -/* - * Memory size exceptions for special cases. Some boards may be set - * for auto memory sizing, but we can't do it that way for some reason. - * For example the 5206eLITE board has static RAM, and auto-detecting - * the SDRAM will do you no good at all. Same goes for the MOD5272. - */ -#ifdef CONFIG_RAMAUTO -#if defined(CONFIG_M5206eLITE) -#define MEM_SIZE 0x00100000 /* 1MiB default memory */ -#endif -#if defined(CONFIG_MOD5272) -#define MEM_SIZE 0x00800000 /* 8MiB default memory */ -#endif -#endif /* CONFIG_RAMAUTO */ - - -/* - * If we don't have a fixed memory size now, then lets build in code + * If we don't have a fixed memory size, then lets build in code * to auto detect the DRAM size. Obviously this is the prefered - * method, and should work for most boards (it won't work for those - * that do not have their RAM starting at address 0). + * method, and should work for most boards. It won't work for those + * that do not have their RAM starting at address 0, and it only + * works on SDRAM (not boards fitted with SRAM). */ -#if defined(MEM_SIZE) +#if CONFIG_RAMSIZE != 0 .macro GET_MEM_SIZE - movel #MEM_SIZE,%d0 /* hard coded memory size */ + movel #CONFIG_RAMSIZE,%d0 /* hard coded memory size */ .endm #elif defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \ @@ -98,37 +66,7 @@ .endm #else -#error "ERROR: I don't know how to determine your boards memory size?" -#endif - - -/* - * Most ColdFire boards have their DRAM starting at address 0. - * Notable exception is the 5206eLITE board, another is the MOD5272. - */ -#if defined(CONFIG_M5206eLITE) -#define MEM_BASE 0x30000000 -#endif -#if defined(CONFIG_MOD5272) -#define MEM_BASE 0x02000000 -#define VBR_BASE 0x20000000 /* vectors in SRAM */ -#endif -#if defined(CONFIG_M5208EVB) -#define MEM_BASE 0x40000000 -#endif - -#ifndef MEM_BASE -#define MEM_BASE 0x00000000 /* memory base at address 0 */ -#endif - -/* - * The default location for the vectors is at the base of RAM. - * Some boards might like to use internal SRAM or something like - * that. If no board specific header defines an alternative then - * use the base of RAM. - */ -#ifndef VBR_BASE -#define VBR_BASE MEM_BASE /* vector address */ +#error "ERROR: I don't know how to probe your boards memory size?" #endif /*****************************************************************************/ @@ -191,11 +129,11 @@ _start: * Create basic memory configuration. Set VBR accordingly, * and size memory. */ - movel #VBR_BASE,%a7 + movel #CONFIG_VECTORBASE,%a7 movec %a7,%VBR /* set vectors addr */ movel %a7,_ramvec - movel #MEM_BASE,%a7 /* mark the base of RAM */ + movel #CONFIG_RAMBASE,%a7 /* mark the base of RAM */ movel %a7,_rambase GET_MEM_SIZE /* macro code determines size */ diff --git a/arch/m68knommu/platform/68328/head-pilot.S b/arch/m68knommu/platform/68328/head-pilot.S index c46775fe04be..46b3604f999c 100644 --- a/arch/m68knommu/platform/68328/head-pilot.S +++ b/arch/m68knommu/platform/68328/head-pilot.S @@ -21,7 +21,6 @@ .global _start .global _rambase -.global __ramvec .global _ramvec .global _ramstart .global _ramend @@ -121,7 +120,7 @@ L0: DBG_PUTC('B') /* Copy command line from beginning of RAM (+16) to end of bss */ - movel #__ramvec, %d7 + movel #CONFIG_VECTORBASE, %d7 addl #16, %d7 moveal %d7, %a0 moveal #_ebss, %a1 diff --git a/arch/m68knommu/platform/68328/head-ram.S b/arch/m68knommu/platform/68328/head-ram.S index 6bdc9bce43f2..e8dc9241ff96 100644 --- a/arch/m68knommu/platform/68328/head-ram.S +++ b/arch/m68knommu/platform/68328/head-ram.S @@ -1,10 +1,7 @@ #include <linux/config.h> .global __main - .global __ram_start - .global __ram_end .global __rom_start - .global __rom_end .global _rambase .global _ramstart @@ -12,6 +9,7 @@ .global splash_bits .global _start .global _stext + .global _edata #define DEBUG #define ROM_OFFSET 0x10C00000 @@ -73,7 +71,7 @@ pclp1: #ifdef CONFIG_RELOCATE /* Copy me to RAM */ moveal #__rom_start, %a0 - moveal #__ram_start, %a1 + moveal #_stext, %a1 moveal #_edata, %a2 /* Copy %a0 to %a1 until %a1 == %a2 */ |