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* ACPICA: Update debug output componentsBob Moore2010-07-061-1/+2
| | | | | | | | Add data table compiler output component Signed-off-by: Bob Moore <robert.moore@intel.com> Signed-off-by: Lin Ming <ming.m.lin@intel.com> Signed-off-by: Len Brown <len.brown@intel.com>
* ACPICA: Add support for WDDT - Watchdog Descriptor TableBob Moore2010-07-061-0/+39
| | | | | | | | Header file support. Signed-off-by: Bob Moore <robert.moore@intel.com> Signed-off-by: Lin Ming <ming.m.lin@intel.com> Signed-off-by: Len Brown <len.brown@intel.com>
* ACPICA: Drop acpi_set_gpeRafael J. Wysocki2010-07-063-63/+1
| | | | | | | | | | | | | | | | The acpi_set_gpe() function is a little awkward, because it doesn't really work as advertised in the "disable" case. Namely, if a GPE has been enabled with acpi_enable_gpe() and triggered a notification to occur, and if acpi_set_gpe() is used to disable it before acpi_ev_asynch_enable_gpe() runs, the GPE will be immediately enabled by the latter as though the acpi_set_gpe() had no effect. Thus, since it's been possible to make all of its callers use alternative operations to disable or enable GPEs, acpi_set_gpe() can be dropped. Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl> Signed-off-by: Len Brown <len.brown@intel.com>
* ACPICA: Use low-level GPE enable during GPE block initializationRafael J. Wysocki2010-07-064-44/+47
| | | | | | | | | | | | | | | | | | | | | The GPE block initialization code in acpi_ev_initialize_gpe_block() uses acpi_set_gpe() to make sure that the GPEs with nonzero runtime counter will remain enabled, but since it already has a struct acpi_gpe_event_info object for each GPE, it might use the low-level GPE enabling function, acpi_clear_and_enable_gpe(), for this purpose. To make that happen, move acpi_clear_and_enable_gpe() to drivers/acpi/acpica/evgpe.c and rename it to acpi_ev_enable_gpe(), modify the two existing users of it accordingly and modify acpi_ev_initialize_gpe_block() to use it instead of acpi_set_gpe() and to check its return value. Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl> Signed-off-by: Len Brown <len.brown@intel.com> Signed-off-by: Bob Moore <robert.moore@intel.com> Signed-off-by: Lin Ming <ming.m.lin@intel.com> Signed-off-by: Len Brown <len.brown@intel.com>
* ACPI / EC: Do not use acpi_set_gpeRafael J. Wysocki2010-07-061-11/+4
| | | | | | | | | | The EC driver is the last user of acpi_set_gpe() and since it is guaranteed that the EC GPE will not be shared, acpi_disable_gpe() and acpi_enable_gpe() may be used for disabling the GPE temporarilty if a GPE storm is detected and re-enabling it during EC transactions. Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl> Signed-off-by: Len Brown <len.brown@intel.com>
* ACPI / EC: Drop suspend and resume routinesRafael J. Wysocki2010-07-061-18/+0
| | | | | | | | | | The suspend and resume routines provided by the EC driver are not really necessary, because the handler of the GPE disabled by them is not going to be executed after suspend_device_irqs() and before resume_device_irqs() anyway. Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl> Signed-off-by: Len Brown <len.brown@intel.com>
* ACPICA: Remove wakeup GPE reference counting which is not usedRafael J. Wysocki2010-07-0612-135/+50
| | | | | | | | | | | | | | | | After the previous patch that introduced acpi_gpe_wakeup() and modified the ACPI suspend and wakeup code to use it, the third argument of acpi_{enable|disable}_gpe() and the GPE wakeup reference counter are not necessary any more. Remove them and modify all of the users of acpi_{enable|disable}_gpe() accordingly. Also drop GPE type constants that aren't used any more. Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl> Signed-off-by: Len Brown <len.brown@intel.com> Signed-off-by: Bob Moore <robert.moore@intel.com> Signed-off-by: Lin Ming <ming.m.lin@intel.com> Signed-off-by: Len Brown <len.brown@intel.com>
* ACPICA: Introduce acpi_gpe_wakeup()Rafael J. Wysocki2010-07-065-20/+84
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ACPICA uses reference counters to avoid disabling GPEs too early in case they have been enabled for many times. This is done separately for runtime and for wakeup, but the wakeup GPE reference counter is not really necessary, because GPEs are only enabled to wake up the system at the hardware level by acpi_enter_sleep_state(). Thus it only is necessary to set the corresponding bits in the wakeup enable masks of these GPEs' registers right before the system enters a sleep state. Moreover, the GPE wakeup enable bits can only be set when the target sleep state of the system is known and they need to be cleared immediately after wakeup regardless of how many wakeup devices are associated with a given GPE. On the basis of the above observations, introduce function acpi_gpe_wakeup() to be used for setting or clearing the enable bit corresponding to a given GPE in its enable register's enable_for_wake mask. Modify the ACPI suspend and wakeup code the use acpi_gpe_wakeup() instead of acpi_{enable|disable}_gpe() to set and clear GPE enable bits in their registers' enable_for_wake masks during system transitions to a sleep state and back to the working state, respectively. [This will allow us to drop the third argument of acpi_{enable|disable}_gpe() and simplify the GPE handling code.] Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl> Signed-off-by: Len Brown <len.brown@intel.com> Signed-off-by: Bob Moore <robert.moore@intel.com> Signed-off-by: Lin Ming <ming.m.lin@intel.com> Signed-off-by: Len Brown <len.brown@intel.com>
* ACPICA: Rename acpi_hw_gpe_register_bitLin Ming2010-07-063-7/+7
| | | | | | | | Rename acpi_hw_gpe_register_bit to acpi_hw_get_gpe_register_bit in order to be same with ACPICA code base. Signed-off-by: Lin Ming <ming.m.lin@intel.com> Signed-off-by: Len Brown <len.brown@intel.com>
* ACPICA: Update version to 20100528Bob Moore2010-07-061-1/+1
| | | | | | | | Version 20100528. Signed-off-by: Bob Moore <robert.moore@intel.com> Signed-off-by: Lin Ming <ming.m.lin@intel.com> Signed-off-by: Len Brown <len.brown@intel.com>
* ACPICA: Add signatures for undefined tables: ATKG, GSCI, IEITBob Moore2010-07-061-0/+9
| | | | | | | | | These ACPI tables have been seen in the field, but the actual table definitions are unkown at this time. Signed-off-by: Bob Moore <robert.moore@intel.com> Signed-off-by: Lin Ming <ming.m.lin@intel.com> Signed-off-by: Len Brown <len.brown@intel.com>
* ACPICA: Optimization: Reduce the number of namespace walksAlexey Starikovskiy2010-07-062-6/+32
| | | | | | | | | | On control method exit, only walk the namespace if the method is known to have created namespace objects outside of its local scope. Signed-off-by: Alexey Starikovskiy <astarikovskiy@suse.de> Signed-off-by: Bob Moore <robert.moore@intel.com> Signed-off-by: Lin Ming <ming.m.lin@intel.com> Signed-off-by: Len Brown <len.brown@intel.com>
* ACPICA: Update flags for operand objectBob Moore2010-07-062-17/+8
| | | | | | | | | | Remove obsolete AOPOBJ_SINGLE_DATUM. Add AOPOBJ_INVALID for use if the host OS rejects the address of an operation region (currently only used by Linux.) Signed-off-by: Bob Moore <robert.moore@intel.com> Signed-off-by: Lin Ming <ming.m.lin@intel.com> Signed-off-by: Len Brown <len.brown@intel.com>
* ACPICA: Performance enhancement for namespace search and accessAlexey Starikovskiy2010-07-0615-218/+52
| | | | | | | | | | | | | | | This change enhances the performance of namespace searches and walks by adding a backpointer to the parent in each namespace node. On large namespaces, this change can improve overall ACPI performance by up to 9X. Adding a pointer to each namespace node increases the overall size of the internal namespace by about 5%, since each namespace entry usually consists of both a namespace node and an ACPI operand object. Signed-off-by: Alexey Starikovskiy <astarikovskiy@suse.de> Signed-off-by: Bob Moore <robert.moore@intel.com> Signed-off-by: Lin Ming <ming.m.lin@intel.com> Signed-off-by: Len Brown <len.brown@intel.com>
* ACPICA: Expand device initialization counters to 32 bitsBob Moore2010-07-062-5/+5
| | | | | | | | | Expand the various device initialization counters from 16-bit to 32-bit. Allows for very large namespaces. Signed-off-by: Bob Moore <robert.moore@intel.com> Signed-off-by: Lin Ming <ming.m.lin@intel.com> Signed-off-by: Len Brown <len.brown@intel.com>
* ACPICA: Core: Replace all %d format specifiers with %u (unsigned)Bob Moore2010-07-0611-28/+28
| | | | | | | | | With only a few exceptions, ACPICA does not use signed integers. Therefore, %d is incorrect. Signed-off-by: Bob Moore <robert.moore@intel.com> Signed-off-by: Lin Ming <ming.m.lin@intel.com> Signed-off-by: Len Brown <len.brown@intel.com>
* ACPICA: Expand initialization counters to 32 bitsAlexey Starikovskiy2010-07-063-24/+24
| | | | | | | | | | Expand the various initialization counters from 16-bit to 32-bit. Allows for very large namespaces. Signed-off-by: Alexey Starikovskiy <astarikovskiy@suse.de> Signed-off-by: Bob Moore <robert.moore@intel.com> Signed-off-by: Lin Ming <ming.m.lin@intel.com> Signed-off-by: Len Brown <len.brown@intel.com>
* ACPICA: iASL/Core: Add support for _WDG/_WED MS methodsBob Moore2010-07-061-6/+7
| | | | | | | | | | | | These objects are defined by "Windows Instrumentation", and are not part of the ACPI spec. Adds compiler support and runtime typechecking support in the ACPICA core. ACPICA BZ 860. http://www.acpica.org/bugzilla/show_bug.cgi?id=860 Signed-off-by: Bob Moore <robert.moore@intel.com> Signed-off-by: Lin Ming <ming.m.lin@intel.com> Signed-off-by: Len Brown <len.brown@intel.com>
* ACPICA: Add comment: _BCL cannot be sorted on the flyBob Moore2010-07-061-0/+7
| | | | | | | | Because of package index values used for _BQC and _BCM. Signed-off-by: Bob Moore <robert.moore@intel.com> Signed-off-by: Lin Ming <ming.m.lin@intel.com> Signed-off-by: Len Brown <len.brown@intel.com>
* Linux 2.6.35-rc4v2.6.35-rc4Linus Torvalds2010-07-041-1/+1
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* Merge master.kernel.org:/home/rmk/linux-2.6-armLinus Torvalds2010-07-0420-61/+113
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * master.kernel.org:/home/rmk/linux-2.6-arm: ARM: 6205/1: perf: ensure counter delta is treated as unsigned ARM: 6202/1: Do not ARM_DMA_MEM_BUFFERABLE on RealView boards with L210/L220 ARM: 6201/1: RealView: Do not use outer_sync() on ARM11MPCore boards with L220 ARM: 6195/1: OMAP3: pmu: make CPU_HAS_PMU dependent on OMAP3_EMU ARM: 6194/1: change definition of cpu_relax() for ARM11MPCore ARM: 6193/1: RealView: Align the machine_desc.phys_io to 1MB section ARM: 6192/1: VExpress: Align the machine_desc.phys_io to 1MB section ARM: 6188/1: Add a config option for the ARM11MPCore DMA cache maintenance workaround ARM: 6187/1: The v6_dma_inv_range() function must preserve data on SMP ARM: 6186/1: Avoid the CONSISTENT_DMA_SIZE warning on noMMU builds ARM: mx3: mx31lilly: fix build error for !CONFIG_USB_ULPI [ARM] mmp: fix build failure due to IRQ_PMU depends on ARCH_PXA [ARM] pxa/mioa701: fix camera regression [ARM] pxa/z2: fix flash layout to final version [ARM] pxa/z2: fix missing include in battery driver [ARM] pxa: fix incorrect gpio type in udc_pxa2xx.h
| * ARM: 6205/1: perf: ensure counter delta is treated as unsignedWill Deacon2010-07-041-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Hardware performance counters on ARM are 32-bits wide but atomic64_t variables are used to represent counter data in the hw_perf_event structure. The armpmu_event_update function right-shifts a signed 64-bit delta variable and adds the result to the event count. This can lead to shifting in sign-bits if the MSB of the 32-bit counter value is set. This results in perf output such as: Performance counter stats for 'sleep 20': 18446744073460670464 cycles <-- 0xFFFFFFFFF12A6000 7783773 instructions # 0.000 IPC 465 context-switches 161 page-faults 1172393 branches 20.154242147 seconds time elapsed This patch ensures that the delta value is treated as unsigned so that the right shift sets the upper bits to zero. Cc: <stable@kernel.org> Acked-by: Jamie Iles <jamie.iles@picochip.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * ARM: 6202/1: Do not ARM_DMA_MEM_BUFFERABLE on RealView boards with L210/L220Catalin Marinas2010-07-021-0/+2
| | | | | | | | | | | | | | | | | | | | | | RealView boards with certain revisions of the L210/L220 cache controller may have issues (hardware deadlock) with the mandatory barriers (DSB followed by an L2 cache sync) when ARM_DMA_MEM_BUFFERABLE is enabled. The patch disables ARM_DMA_MEM_BUFFERABLE for these boards. Tested-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * ARM: 6201/1: RealView: Do not use outer_sync() on ARM11MPCore boards with L220Catalin Marinas2010-07-022-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | RealView boards with certain revisions of the L220 cache controller (ARM11* processors only) may have issues (hardware deadlock) with the recent changes to the mb() barrier implementation (DSB followed by an L2 cache sync). The patch redefines the RealView ARM11MPCore mandatory barriers without the outer_sync() call. Cc: <stable@kernel.org> Tested-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * Merge branch 'imx-for-2.6.35' of git://git.pengutronix.de/git/imx/linux-2.6Russell King2010-07-011-11/+22
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| | * ARM: mx3: mx31lilly: fix build error for !CONFIG_USB_ULPIDaniel Mack2010-07-011-11/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | arch/arm/mach-mx3/built-in.o: In function `mx31lilly_board_init': mach-kzm_arm11_01.c:(.init.text+0x674): undefined reference to `otg_ulpi_create' mach-kzm_arm11_01.c:(.init.text+0x68c): undefined reference to `otg_ulpi_create' mach-kzm_arm11_01.c:(.init.text+0x744): undefined reference to `mxc_ulpi_access_ops' make: *** [.tmp_vmlinux1] Error 1 Signed-off-by: Daniel Mack <daniel@caiaq.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | Merge branch 'fix' of ↵Russell King2010-07-015-29/+18
| |\ \ | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/ycmiao/pxa-linux-2.6
| | * | [ARM] mmp: fix build failure due to IRQ_PMU depends on ARCH_PXAJonathan Cameron2010-06-141-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PMU is not tested and enabled on MMP architecture at this moment, the device IRQ number, IRQ_PMU depends on ARCH_PXA. Build PMU only for ARCH_PXA. Signed-off-by: Jonathan Cameron <jic23@cam.ac.uk> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
| | * | [ARM] pxa/mioa701: fix camera regressionRobert Jarzmik2010-06-131-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since commit a48c24a696f0d93c49f913b7818e9819612b1f4e, the camera is not working anymore. After the v4l2 migration, the mt9m111 camera board information was not passed to the i2c layer anymore, but stored for future use of v4l2 (through soc_camera). Because mioa701_i2c_devices[] was tagged as "__initdata", and because after the v4l2 migration, the new structure "iclink" references it, the mt9m111 driver is not probed anymore, as part of "iclink" is not valid (discarded after kernel init). Although there is not compilation error, nor runtime oops, this patch restores a working camera on the mioa701 board. Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr> Acked-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
| | * | [ARM] pxa/z2: fix flash layout to final versionMarek Vasut2010-06-131-16/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes flash layout to it's final version. Also, I fixed the authorship information of this file as it's been totally reworked since Ken released his last version. Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
| | * | [ARM] pxa/z2: fix missing include in battery driverMarek Vasut2010-06-131-9/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove redundant includes and add slab.h to fix problem with building. Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
| | * | [ARM] pxa: fix incorrect gpio type in udc_pxa2xx.hSteve Bennett2010-06-131-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | gpio must be int, not u16, otherwise -1 isn't recognised by gpio_is_valid(). Signed-off-by: Steve Bennett <steveb@workware.net.au> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
| * | | ARM: 6195/1: OMAP3: pmu: make CPU_HAS_PMU dependent on OMAP3_EMUWill Deacon2010-07-011-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CPU performance event counters on v7 cores will only operate if either the NIDEN or DBGEN signals are driven high. For the OMAP3 platform, these signals are driven low by default but DBGEN can be asserted by selecting the OMAP3_EMU Kconfig option, which enables the virtual clock for hardware debugging peripherals. Acked-by: Jean Pihet <jpihet@mvista.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | | ARM: 6194/1: change definition of cpu_relax() for ARM11MPCoreWill Deacon2010-07-011-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Linux expects that if a CPU modifies a memory location, then that modification will eventually become visible to other CPUs in the system. On an ARM11MPCore processor, loads are prioritised over stores so it is possible for a store operation to be postponed if a polling loop immediately follows it. If the variable being polled indirectly depends on the outstanding store [for example, another CPU may be polling the variable that is pending modification] then there is the potential for deadlock if interrupts are disabled. This deadlock occurs in the KGDB testsuire when executing on an SMP ARM11MPCore configuration. This patch changes the definition of cpu_relax() to smp_mb() for ARMv6 cores, forcing a flushing of the write buffer on SMP systems before the next load takes place. If the Kernel is not compiled for SMP support, this will expand to a barrier() as before. Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | | ARM: 6193/1: RealView: Align the machine_desc.phys_io to 1MB sectionCatalin Marinas2010-07-015-5/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When not aligned, random bits could be written in the initial page table by the __create_page_tables() function. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | | ARM: 6192/1: VExpress: Align the machine_desc.phys_io to 1MB sectionCatalin Marinas2010-07-011-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When not aligned, random bits could be written in the initial page table by the __create_page_tables() function. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | | ARM: 6188/1: Add a config option for the ARM11MPCore DMA cache maintenance ↵Catalin Marinas2010-07-012-3/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | workaround Commit f4d6477f introduced a workaround for the lack of hardware broadcasting of the cache maintenance operations on ARM11MPCore. However, the workaround is only valid on CPUs that do not do speculative loads into the D-cache. This patch adds a Kconfig option with the corresponding help to make the above clear. When the DMA_CACHE_RWFO option is disabled, the kernel behaviour is that prior to the f4d6477f commit. This also allows ARMv6 UP processors with speculative loads to work correctly. For other processors, a different workaround may be needed. Cc: Ronen Shitrit <rshitrit@marvell.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | | ARM: 6187/1: The v6_dma_inv_range() function must preserve data on SMPCatalin Marinas2010-07-011-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A recent patch for DMA cache maintenance on ARM11MPCore added a write for ownership trick to the v6_dma_inv_range() function. Such operation destroys data already present in the buffer. However, this function is used with with dma_sync_single_for_device() which is supposed to preserve the existing data transfered into the buffer. This patch adds a combination of read/write for ownership to preserve the original data. Reported-by: Ronen Shitrit <rshitrit@marvell.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | | ARM: 6186/1: Avoid the CONSISTENT_DMA_SIZE warning on noMMU buildsCatalin Marinas2010-07-011-9/+9
| | |/ | |/| | | | | | | | | | | | | | | | | | | This macro is not defined when !CONFIG_MMU so this patch moves the CONSISTENT_* definitions to the CONFIG_MMU section. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | | Merge branch 'perf-fixes-for-linus' of ↵Linus Torvalds2010-07-043-4/+22
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip * 'perf-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip: perf, x86: Fix incorrect branches event on AMD CPUs perf tools: Fix find tids routine by excluding "." and ".." x86: Send a SIGTRAP for user icebp traps
| * | | perf, x86: Fix incorrect branches event on AMD CPUsVince Weaver2010-07-031-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | While doing some performance counter validation tests on some assembly language programs I noticed that the "branches:u" count was very wrong on AMD machines. It looks like the wrong event was selected. Signed-off-by: Vince Weaver <vweaver1@eecs.utk.edu> Acked-by: Peter Zijlstra <a.p.zijlstra@chello.nl> Cc: Paul Mackerras <paulus@samba.org> Cc: Arnaldo Carvalho de Melo <acme@redhat.com> Cc: Robert Richter <robert.richter@amd.com> Cc: Borislav Petkov <borislav.petkov@amd.com> Cc: Frederic Weisbecker <fweisbec@gmail.com> Cc: <stable@kernel.org> LKML-Reference: <alpine.DEB.2.00.1007011526010.23160@cl320.eecs.utk.edu> Signed-off-by: Ingo Molnar <mingo@elte.hu>
| * | | perf tools: Fix find tids routine by excluding "." and ".."Gui Jianfeng2010-07-011-1/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Introduce a filter function to skip "." and ".." directories when calculating tid number, otherwise tid 0 will be included in the all_tid result array. Cc: Ingo Molnar <mingo@elte.hu> LKML-Reference: <4C185F68.1020505@cn.fujitsu.com> Signed-off-by: Gui Jianfeng <guijianfeng@cn.fujitsu.com> Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
| * | | x86: Send a SIGTRAP for user icebp trapsFrederic Weisbecker2010-06-301-1/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before we had a generic breakpoint layer, x86 used to send a sigtrap for any debug event that happened in userspace, except if it was caused by lazy dr7 switches. Currently we only send such signal for single step or breakpoint events. However, there are three other kind of debug exceptions: - debug register access detected: trigger an exception if the next instruction touches the debug registers. We don't use it. - task switch, but we don't use tss. - icebp/int01 trap. This instruction (0xf1) is undocumented and generates an int 1 exception. Unlike single step through TF flag, it doesn't set the single step origin of the exception in dr6. icebp then used to be reported in userspace using trap signals but this have been incidentally broken with the new breakpoint code. Reenable this. Since this is the only debug event that doesn't set anything in dr6, this is all we have to check. This fixes a regression in Wine where World Of Warcraft got broken as it uses this for software protection checks purposes. And probably other apps do. Reported-and-tested-by: Alexandre Julliard <julliard@winehq.org> Signed-off-by: Frederic Weisbecker <fweisbec@gmail.com> Cc: Ingo Molnar <mingo@elte.hu> Cc: H. Peter Anvin <hpa@zytor.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Prasad <prasad@linux.vnet.ibm.com> Cc: 2.6.33.x 2.6.34.x <stable@kernel.org>
* | | | module: initialize module dynamic debug laterYehuda Sadeh2010-07-043-11/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We should initialize the module dynamic debug datastructures only after determining that the module is not loaded yet. This fixes a bug that introduced in 2.6.35-rc2, where when a trying to load a module twice, we also load it's dynamic printing data twice which causes all sorts of nasty issues. Also handle the dynamic debug cleanup later on failure. Signed-off-by: Yehuda Sadeh <yehuda@hq.newdream.net> Signed-off-by: Rusty Russell <rusty@rustcorp.com.au> (removed a #ifdef) Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* | | | Merge branch 'for-linus' of git://oss.sgi.com/xfs/xfsLinus Torvalds2010-07-0417-388/+172
|\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'for-linus' of git://oss.sgi.com/xfs/xfs: xfs: remove block number from inode lookup code xfs: rename XFS_IGET_BULKSTAT to XFS_IGET_UNTRUSTED xfs: validate untrusted inode numbers during lookup xfs: always use iget in bulkstat xfs: prevent swapext from operating on write-only files
| * | | | xfs: remove block number from inode lookup codeDave Chinner2010-06-2415-59/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The block number comes from bulkstat based inode lookups to shortcut the mapping calculations. We ar enot able to trust anything from bulkstat, so drop the block number as well so that the correct lookups and mappings are always done. Signed-off-by: Dave Chinner <dchinner@redhat.com> Reviewed-by: Christoph Hellwig <hch@lst.de>
| * | | | xfs: rename XFS_IGET_BULKSTAT to XFS_IGET_UNTRUSTEDDave Chinner2010-06-245-12/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Inode numbers may come from somewhere external to the filesystem (e.g. file handles, bulkstat information) and so are inherently untrusted. Rename the flag we use for these lookups to make it obvious we are doing a lookup of an untrusted inode number and need to verify it completely before trying to read it from disk. Signed-off-by: Dave Chinner <dchinner@redhat.com> Reviewed-by: Christoph Hellwig <hch@lst.de>
| * | | | xfs: validate untrusted inode numbers during lookupDave Chinner2010-06-241-43/+78
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When we decode a handle or do a bulkstat lookup, we are using an inode number we cannot trust to be valid. If we are deleting inode chunks from disk (default noikeep mode), then we cannot trust the on disk inode buffer for any given inode number to correctly reflect whether the inode has been unlinked as the di_mode nor the generation number may have been updated on disk. This is due to the fact that when we delete an inode chunk, we do not write the clusters back to disk when they are removed - instead we mark them stale to avoid them being written back potentially over the top of something that has been subsequently allocated at that location. The result is that we can have locations of disk that look like they contain valid inodes but in reality do not. Hence we cannot simply convert the inode number to a block number and read the location from disk to determine if the inode is valid or not. As a result, and XFS_IGET_BULKSTAT lookup needs to actually look the inode up in the inode allocation btree to determine if the inode number is valid or not. It should be noted even on ikeep filesystems, there is the possibility that blocks on disk may look like valid inode clusters. e.g. if there are filesystem images hosted on the filesystem. Hence even for ikeep filesystems we really need to validate that the inode number is valid before issuing the inode buffer read. Signed-off-by: Dave Chinner <dchinner@redhat.com> Reviewed-by: Christoph Hellwig <hch@lst.de>
| * | | | xfs: always use iget in bulkstatChristoph Hellwig2010-06-236-282/+59
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The non-coherent bulkstat versionsthat look directly at the inode buffers causes various problems with performance optimizations that make increased use of just logging inodes. This patch makes bulkstat always use iget, which should be fast enough for normal use with the radix-tree based inode cache introduced a while ago. Signed-off-by: Christoph Hellwig <hch@lst.de> Reviewed-by: Dave Chinner <dchinner@redhat.com>
| * | | | xfs: prevent swapext from operating on write-only filesDan Rosenberg2010-06-241-1/+4
| | |_|/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch prevents user "foo" from using the SWAPEXT ioctl to swap a write-only file owned by user "bar" into a file owned by "foo" and subsequently reading it. It does so by checking that the file descriptors passed to the ioctl are also opened for reading. Signed-off-by: Dan Rosenberg <dan.j.rosenberg@gmail.com> Reviewed-by: Christoph Hellwig <hch@lst.de>
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