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path: root/arch/mips/kernel/octeon_switch.S
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* Kbuild: rename CC_STACKPROTECTOR[_STRONG] config variablesLinus Torvalds2018-06-141-1/+1
* MIPS: Move r4k FP code from r4k_switch.S to r4k_fpu.SPaul Burton2017-08-291-5/+6
* MIPS: Fix octeon FP context switch handlingPaul Burton2015-10-021-25/+1
* MIPS: OCTEON: Delete unused COP2 saving codeAleksey Makarov2015-02-201-26/+0
* MIPS: OCTEON: Use correct instruction to read 64-bit COP0 registerChandrakala Chavva2015-02-201-3/+3
* MIPS: OCTEON: Save and restore CP2 SHA3 stateDavid Daney2015-02-201-11/+32
* MIPS: OCTEON: Fix FP context save.David Daney2015-02-201-12/+7
* MIPS: OCTEON: Save/Restore wider multiply registers in OCTEON III CPUsDavid Daney2015-02-201-30/+98
* MIPS: OCTEON: Enable use of FPUDavid Daney2014-05-301-23/+61
* MIPS: stack protector: Fix per-task canary switchJames Hogan2013-10-071-1/+1
* MIPS: r4k,octeon,r2300: stack protector: change canary per taskGregory Fong2013-07-011-0/+7
* MIPS: Move cop2 save/restore to switch_to()Jayachandran C2013-06-131-27/+0
* MIPS: Whitespace cleanup.Ralf Baechle2013-02-011-52/+52
* MIPS: Don't include <asm/page.h> unnecessarily.Ralf Baechle2012-12-281-1/+0
* MIPS: Fix race condition with FPU thread task flag during context switch.Leonid Yegoshin2012-07-191-1/+1
* update David Miller's old email addressJustin P. Mattock2011-04-061-1/+1
* MIPS: Nuke trailing blank linesRalf Baechle2010-02-271-1/+0
* MIPS: Consolidate all CONFIG_CPU_HAS_LLSC use in a single C file.Ralf Baechle2009-09-171-3/+0
* MIPS: Add Cavium OCTEON processor support files to arch/mips/cavium-octeon.David Daney2009-01-111-0/+506
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