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* x86/speculation/l1tf: Exempt zeroed PTEs from inversionSean Christopherson2018-08-181-1/+10
* x86/mm: Add TLB purge to free pmd/pte page interfacesToshi Kani2018-08-171-6/+30
* ioremap: Update pgtable free interfaces with addrChintan Pandya2018-08-171-5/+7
* crypto: x86/sha256-mb - fix digest copy in sha256_mb_mgr_get_comp_job_avx2()Eric Biggers2018-08-171-1/+1
* x86/mm: Disable ioremap free page handling on x86-PAEToshi Kani2018-08-171-0/+19
* xen/pv: Call get_cpu_address_sizes to set x86_virt/phys_bitsM. Vefa Bicakci2018-08-173-1/+5
* x86/mm/pti: Clear Global bit more aggressivelyDave Hansen2018-08-172-10/+30
* x86/platform/UV: Mark memblock related init code and data correctlyDou Liyang2018-08-171-2/+2
* x86/hyper-v: Check for VP_INVAL in hyperv_flush_tlb_others()Vitaly Kuznetsov2018-08-171-0/+5
* x86: i8259: Add missing include fileGuenter Roeck2018-08-171-0/+1
* x86/l1tf: Fix build error seen if CONFIG_KVM_INTEL is disabledGuenter Roeck2018-08-171-2/+1
* x86/init: fix build with CONFIG_SWAP=nVlastimil Babka2018-08-151-0/+2
* x86/smp: fix non-SMP broken build due to redefinition of apic_id_is_primary_t...Vlastimil Babka2018-08-151-0/+2
* x86/microcode: Allow late microcode loading with SMT disabledJosh Poimboeuf2018-08-151-4/+12
* x86/mm/kmmio: Make the tracer robust against L1TFAndi Kleen2018-08-151-10/+15
* x86/mm/pat: Make set_memory_np() L1TF safeAndi Kleen2018-08-151-4/+4
* x86/speculation/l1tf: Make pmd/pud_mknotpresent() invertAndi Kleen2018-08-151-10/+12
* x86/speculation/l1tf: Invert all not present mappingsAndi Kleen2018-08-151-1/+1
* cpu/hotplug: Fix SMT supported evaluationThomas Gleixner2018-08-151-1/+1
* KVM: VMX: Tell the nested hypervisor to skip L1D flush on vmentryPaolo Bonzini2018-08-153-3/+27
* x86/speculation: Use ARCH_CAPABILITIES to skip L1D flush on vmentryPaolo Bonzini2018-08-154-0/+13
* x86/speculation: Simplify sysfs report of VMX L1TF vulnerabilityPaolo Bonzini2018-08-151-3/+9
* x86/KVM/VMX: Don't set l1tf_flush_l1d from vmx_handle_external_intr()Nicolai Stange2018-08-151-1/+0
* x86/irq: Let interrupt handlers set kvm_cpu_l1tf_flush_l1dNicolai Stange2018-08-153-0/+5
* x86: Don't include linux/irq.h from asm/hardirq.hNicolai Stange2018-08-1520-2/+19
* x86/KVM/VMX: Introduce per-host-cpu analogue of l1tf_flush_l1dNicolai Stange2018-08-152-4/+36
* x86/irq: Demote irq_cpustat_t::__softirq_pending to u16Nicolai Stange2018-08-151-1/+1
* x86/KVM/VMX: Move the l1tf_flush_l1d test to vmx_l1d_flush()Nicolai Stange2018-08-151-4/+6
* x86/KVM/VMX: Replace 'vmx_l1d_flush_always' with 'vmx_l1d_flush_cond'Nicolai Stange2018-08-151-5/+5
* x86/KVM/VMX: Don't set l1tf_flush_l1d to true from vmx_l1d_flush()Nicolai Stange2018-08-151-7/+7
* x86/KVM/VMX: Initialize the vmx_l1d_flush_pages' contentNicolai Stange2018-08-151-3/+14
* x86/bugs, kvm: Introduce boot-time control of L1TF mitigationsJiri Kosina2018-08-153-13/+99
* cpu/hotplug: Set CPU_SMT_NOT_SUPPORTED earlyThomas Gleixner2018-08-151-0/+6
* x86/kvm: Allow runtime control of L1D flushThomas Gleixner2018-08-152-6/+9
* x86/kvm: Serialize L1D flush parameter setterThomas Gleixner2018-08-151-2/+6
* x86/kvm: Add static key for flush alwaysThomas Gleixner2018-08-151-5/+11
* x86/kvm: Move l1tf setup functionThomas Gleixner2018-08-151-47/+78
* x86/l1tf: Handle EPT disabled state properThomas Gleixner2018-08-153-45/+54
* x86/kvm: Drop L1TF MSR list approachThomas Gleixner2018-08-151-36/+7
* x86/litf: Introduce vmx status variableThomas Gleixner2018-08-153-13/+54
* x86/KVM/VMX: Use MSR save list for IA32_FLUSH_CMD if requiredKonrad Rzeszutek Wilk2018-08-151-5/+37
* x86/KVM/VMX: Extend add_atomic_switch_msr() to allow VMENTER only MSRsKonrad Rzeszutek Wilk2018-08-151-8/+14
* x86/KVM/VMX: Separate the VMX AUTOLOAD guest/host number accountingKonrad Rzeszutek Wilk2018-08-151-10/+19
* x86/KVM/VMX: Add find_msr() helper functionKonrad Rzeszutek Wilk2018-08-151-13/+18
* x86/KVM/VMX: Split the VMX MSR LOAD structures to have an host/guest numbersKonrad Rzeszutek Wilk2018-08-151-30/+35
* x86/KVM/VMX: Add L1D flush logicPaolo Bonzini2018-08-154-1/+34
* x86/KVM/VMX: Add L1D MSR based flushPaolo Bonzini2018-08-152-4/+17
* x86/KVM/VMX: Add L1D flush algorithmPaolo Bonzini2018-08-151-5/+66
* x86/KVM/VMX: Add module argument for L1TF mitigationKonrad Rzeszutek Wilk2018-08-151-0/+59
* x86/KVM: Warn user if KVM is loaded SMT and L1TF CPU bug being presentKonrad Rzeszutek Wilk2018-08-151-0/+13
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