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path: root/drivers/clk/st/clkgen-pll.c
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* clk: st: STiH407: Support for clockgenA9Gabriel FERNANDEZ2014-07-281-0/+16
| | | | | | | | | | The patch added support for DT registration of ClockGenA9 It includes c32 type PLL. Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org> Signed-off-by: Olivier Bideau <olivier.bideau@st.com> Acked-by: Peter Griffin <peter.griffin@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: st: STiH407: Support for clockgenC0Gabriel FERNANDEZ2014-07-281-0/+32
| | | | | | | | | | The patch added support for DT registration of ClockGenC0 It includes 2 c32 type PLL and a 660 Quadfs. Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org> Signed-off-by: Olivier Bideau <olivier.bideau@st.com> Acked-by: Peter Griffin <peter.griffin@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: st: STiH407: Support for clockgenA0Gabriel FERNANDEZ2014-07-281-0/+16
| | | | | | | | | The patch added support for DT registration of ClockGenA0 It includes c32 type PLL. Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org> Signed-off-by: Olivier Bideau <olivier.bideau@st.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: st: use static const for clkgen_pll_data tablesGabriel FERNANDEZ2014-07-281-16/+14
| | | | | | | converts clkgen_pll_data tables into static const Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: st: Terminate of match tableStephen Boyd2014-05-281-0/+1
| | | | | | | | | Failure to terminate this match table can lead to boot failures depending on where the compiler places the match table. Cc: Gabriel FERNANDEZ <gabriel.fernandez@st.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: st: Fix memory leakValentin Ilie2014-05-231-1/+3
| | | | | | | When it fails to allocate div, gate should be free'd before return Signed-off-by: Valentin Ilie <valentin.ilie@gmail.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: st: Support for ClockGenA9/DDR/GPUGabriel FERNANDEZ2014-03-251-0/+139
| | | | | | | | | | | | | | The patch added support for DT registration of ClockGenA9/DDR/GPU ClockgenA9/DDR : It includes c32 type PLL (also in ClockgenA1x), hence only CLK_OF_DECLARE implementation is required. ClockgenGPU : It includes c65 type PLL (also in ClockgenAx), hence only CLK_OF_DECLARE implementation is required. Signed-off-by: Pankaj Dev <pankaj.dev@st.com> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: st: Support for PLLs inside ClockGenA(s)Gabriel FERNANDEZ2014-03-251-0/+559
The patch supports the c65/c32 type PLLs used by ClockGenA(s) PLL clock : It includes support for all c65/c32 type PLLs inside ClockGenA(s) : implemented as Fixed Parent / Fixed Rate clock, with clock rate calculated reading H/w settings done at BOOT. c65 PLLs have 2 outputs : HS and LS c32 PLLs have 1-4 outputs : ODFx Signed-off-by: Pankaj Dev <pankaj.dev@st.com> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
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