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* clk: ingenic: Fix doc of ingenic_cgu_div_infoPaul Cercueil2019-03-231-1/+1
* clk: ingenic: Fix round_rate misbehaving with non-integer dividersPaul Cercueil2019-03-231-5/+5
* clk: clk-twl6040: Fix imprecise external abort for pdmclkTony Lindgren2019-03-231-2/+51
* clk: sunxi: A31: Fix wrong AHB gate numberAndre Przywara2019-03-231-2/+2
* clk: imx6sl: ensure MMDC CH0 handshake is bypassedAnson Huang2019-02-121-0/+6
* clk: sunxi-ng: a33: Set CLK_SET_RATE_PARENT for all audio module clocksChen-Yu Tsai2019-02-121-3/+3
* clk: imx6q: reset exclusive gates on initLucas Stach2019-01-261-1/+5
* clk: rockchip: fix typo in rk3188 spdif_frac parentJohan Jonker2019-01-091-1/+1
* clk: mmp: Off by one in mmp_clk_add()Dan Carpenter2018-12-211-1/+1
* clk: mvebu: Off by one bugs in cp110_of_clk_get()Dan Carpenter2018-12-211-2/+2
* clk: fixed-factor: fix of_node_get-put imbalanceRicardo Ribalda Delgado2018-11-271-0/+1
* clk: samsung: exynos5420: Enable PERIS clocks for suspendMarek Szyprowski2018-11-271-0/+1
* clk: fixed-rate: fix of_node_get-put imbalanceAlan Tull2018-11-271-0/+1
* reset: hisilicon: fix potential NULL pointer dereferenceGustavo A. R. Silva2018-11-211-3/+2
* clk: rockchip: Fix static checker warning in rockchip_ddrclk_get_parent callEnric Balletbo i Serra2018-11-211-4/+0
* clk: at91: Fix division by zero in PLL recalc_rate()Ronald Wahl2018-11-211-0/+3
* clk: s2mps11: Fix matching when built as module and DT node contains compatibleKrzysztof Kozlowski2018-11-211-0/+30
* clk: samsung: Fix m2m scaler clock on Exynos542xAndrzej Pietrasiewicz2018-11-101-1/+1
* clk: clk-fixed-factor: Clear OF_POPULATED flag in case of failureRajan Vaja2018-09-261-1/+8
* clk: imx6ul: fix missing of_node_put()Nicholas Mc Guire2018-09-261-0/+1
* clk: rockchip: Add pclk_rkpwm_pmu to PMU critical clocks in rk3399Levin Du2018-09-151-0/+1
* clk: rockchip: fix clk_i2sout parent selection bits on rk3399Alberto Panizzo2018-09-051-1/+1
* clk: at91: PLL recalc_rate() now using cached MUL and DIV valuesMarcin Ziemianowicz2018-07-031-12/+1
* clk: renesas: cpg-mssr: Stop using printk format %pCrGeert Uytterhoeven2018-07-031-4/+5
* clk: samsung: exynos3250: Fix PLL ratesAndrzej Hajda2018-05-251-2/+2
* clk: samsung: exynos5250: Fix PLL ratesAndrzej Hajda2018-05-251-4/+4
* clk: samsung: exynos5433: Fix PLL ratesAndrzej Hajda2018-05-251-6/+6
* clk: samsung: exynos5260: Fix PLL ratesAndrzej Hajda2018-05-251-1/+1
* clk: samsung: exynos7: Fix PLL ratesAndrzej Hajda2018-05-251-1/+1
* clk: samsung: s3c2410: Fix PLL ratesAndrzej Hajda2018-05-251-8/+8
* clk: rockchip: Prevent calculating mmc phase if clock rate is zeroShawn Lin2018-05-251-0/+23
* clk: tegra: Fix pll_u rate configurationMarcel Ziswiler2018-05-251-0/+2
* clk: Don't show the incorrect clock phaseShawn Lin2018-05-251-0/+3
* clk: rockchip: Fix wrong parent for SDMMC phase clock for rk3228Shawn Lin2018-05-251-1/+1
* clk: bcm2835: De-assert/assert PLL reset signal when appropriateBoris Brezillon2018-04-241-3/+5
* clk: fix false-positive Wmaybe-uninitialized warningArnd Bergmann2018-04-241-3/+3
* clk: mvebu: armada-38x: add support for missing clocksRichard Genoud2018-04-241-7/+7
* clk: mvebu: armada-38x: add support for 1866MHz variantsRalph Sennhauser2018-04-241-3/+4
* clk: at91: fix clk-generated compilationAlexandre Belloni2018-04-131-0/+1
* clk: meson: meson8b: add compatibles for Meson8 and Meson8m2Martin Blumenstingl2018-04-132-4/+7
* clk: Fix __set_clk_rates error print-stringBryan O'Donoghue2018-04-131-1/+1
* clk: scpi: fix return type of __scpi_dvfs_round_rateSudeep Holla2018-04-131-3/+3
* clk: at91: fix clk-generated parentingAlexandre Belloni2018-04-131-2/+1
* clk: renesas: rcar-gen2: Fix PLL0 on R-Car V2H and E2Geert Uytterhoeven2018-04-131-4/+19
* clk: sunxi-ng: a31: Fix CLK_OUT_* clock opsChen-Yu Tsai2018-03-281-3/+3
* clk: bcm2835: Protect sections updating shared registersBoris Brezillon2018-03-281-0/+4
* clk: bcm2835: Fix ana->maskX definitionsBoris Brezillon2018-03-281-4/+4
* clk: migrate the count of orphaned clocks at initJerome Brunet2018-03-241-16/+21
* clk: si5351: Rename internal plls to avoid name collisionsSergej Sawazki2018-03-241-1/+1
* clk: axi-clkgen: Correctly handle nocount bit in recalc_rate()Lars-Peter Clausen2018-03-241-5/+24
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