From 678bc9a2eabb7f444ef8ad1cfc5ef394e2bd8bf2 Mon Sep 17 00:00:00 2001 From: Vishwanath BS Date: Mon, 22 Feb 2010 22:09:09 -0700 Subject: OMAP3 clock: Introduce 3630 DPLL4 HSDivider changes Divider (M2, M3, M4, M5 and M6) field width has been increased by 1 bit in 3630. This patch has changes to accommodate this in CM dynamically based on chip version. Basically new clock nodes have been added for 3630 DPLL4 M2,M3,M4,M5 and M6 and value of these nodes are used if cpu type is 3630. Signed-off-by: Vishwanath BS [paul@pwsan.com: updated to apply on 2.6.34 queue; comments added] Signed-off-by: Paul Walmsley --- arch/arm/mach-omap2/cm-regbits-34xx.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm/mach-omap2/cm-regbits-34xx.h') diff --git a/arch/arm/mach-omap2/cm-regbits-34xx.h b/arch/arm/mach-omap2/cm-regbits-34xx.h index 29cd13b838ca..e6a724cc63f1 100644 --- a/arch/arm/mach-omap2/cm-regbits-34xx.h +++ b/arch/arm/mach-omap2/cm-regbits-34xx.h @@ -542,6 +542,7 @@ /* CM_CLKSEL3_PLL */ #define OMAP3430_DIV_96M_SHIFT 0 #define OMAP3430_DIV_96M_MASK (0x1f << 0) +#define OMAP3630_DIV_96M_MASK (0x3f << 0) /* CM_CLKSEL4_PLL */ #define OMAP3430ES2_PERIPH2_DPLL_MULT_SHIFT 8 @@ -588,8 +589,10 @@ /* CM_CLKSEL_DSS */ #define OMAP3430_CLKSEL_TV_SHIFT 8 #define OMAP3430_CLKSEL_TV_MASK (0x1f << 8) +#define OMAP3630_CLKSEL_TV_MASK (0x3f << 8) #define OMAP3430_CLKSEL_DSS1_SHIFT 0 #define OMAP3430_CLKSEL_DSS1_MASK (0x1f << 0) +#define OMAP3630_CLKSEL_DSS1_MASK (0x3f << 0) /* CM_SLEEPDEP_DSS specific bits */ @@ -617,6 +620,7 @@ /* CM_CLKSEL_CAM */ #define OMAP3430_CLKSEL_CAM_SHIFT 0 #define OMAP3430_CLKSEL_CAM_MASK (0x1f << 0) +#define OMAP3630_CLKSEL_CAM_MASK (0x3f << 0) /* CM_SLEEPDEP_CAM specific bits */ @@ -712,6 +716,7 @@ /* CM_CLKSEL1_EMU */ #define OMAP3430_DIV_DPLL4_SHIFT 24 #define OMAP3430_DIV_DPLL4_MASK (0x1f << 24) +#define OMAP3630_DIV_DPLL4_MASK (0x3f << 24) #define OMAP3430_DIV_DPLL3_SHIFT 16 #define OMAP3430_DIV_DPLL3_MASK (0x1f << 16) #define OMAP3430_CLKSEL_TRACECLK_SHIFT 11 -- cgit v1.2.1