From bfabbcc679e86cfcaf0e7fd41563f14c29bc74d4 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Mon, 10 Jun 2013 18:19:46 +0900 Subject: ARM: shmobile: Add SCU boot function using argument Add a shmoible_boot_scu function that assumes that the base address of the SCU is passed in r0. This code is free from inline virtual to physical address conversion. Signed-off-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/headsmp-scu.S | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'arch/arm/mach-shmobile/headsmp-scu.S') diff --git a/arch/arm/mach-shmobile/headsmp-scu.S b/arch/arm/mach-shmobile/headsmp-scu.S index 7d113f898e7f..c5c9106bf6c4 100644 --- a/arch/arm/mach-shmobile/headsmp-scu.S +++ b/arch/arm/mach-shmobile/headsmp-scu.S @@ -51,6 +51,19 @@ ENTRY(shmobile_secondary_vector_scu) 2: .long shmobile_scu_base - PAGE_OFFSET + PLAT_PHYS_OFFSET ENDPROC(shmobile_secondary_vector_scu) +ENTRY(shmobile_boot_scu) + @ r0 = SCU base address + mrc p15, 0, r1, c0, c0, 5 @ read MIPDR + and r1, r1, #3 @ mask out cpu ID + lsl r1, r1, #3 @ we will shift by cpu_id * 8 bits + ldr r2, [r0, #8] @ SCU Power Status Register + mov r3, #3 + bic r2, r2, r3, lsl r1 @ Clear bits of our CPU (Run Mode) + str r2, [r0, #8] @ write back + + b shmobile_invalidate_start +ENDPROC(shmobile_boot_scu) + .text .globl shmobile_scu_base shmobile_scu_base: -- cgit v1.2.1 From 4f6da36f7edd57901638df84d1dcbece28831334 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Mon, 10 Jun 2013 18:20:25 +0900 Subject: ARM: shmobile: Remove old SCU boot code Remove shmobile_secondary_vector_scu now when all SCU enabled SMP platforms instead make use of shmobile_boot_scu. This removes two inline virtual to physical address conversions. Signed-off-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/headsmp-scu.S | 22 +--------------------- 1 file changed, 1 insertion(+), 21 deletions(-) (limited to 'arch/arm/mach-shmobile/headsmp-scu.S') diff --git a/arch/arm/mach-shmobile/headsmp-scu.S b/arch/arm/mach-shmobile/headsmp-scu.S index c5c9106bf6c4..6f9865467258 100644 --- a/arch/arm/mach-shmobile/headsmp-scu.S +++ b/arch/arm/mach-shmobile/headsmp-scu.S @@ -25,32 +25,12 @@ __CPUINIT /* - * Reset vector for secondary CPUs. + * Boot code for secondary CPUs. * * First we turn on L1 cache coherency for our CPU. Then we jump to * shmobile_invalidate_start that invalidates the cache and hands over control * to the common ARM startup code. - * This function will be mapped to address 0 by the SBAR register. - * A normal branch is out of range here so we need a long jump. We jump to - * the physical address as the MMU is still turned off. */ - .align 12 -ENTRY(shmobile_secondary_vector_scu) - mrc p15, 0, r0, c0, c0, 5 @ read MIPDR - and r0, r0, #3 @ mask out cpu ID - lsl r0, r0, #3 @ we will shift by cpu_id * 8 bits - ldr r1, 2f - ldr r1, [r1] @ SCU base address - ldr r2, [r1, #8] @ SCU Power Status Register - mov r3, #3 - bic r2, r2, r3, lsl r0 @ Clear bits of our CPU (Run Mode) - str r2, [r1, #8] @ write back - - ldr pc, 1f -1: .long shmobile_invalidate_start - PAGE_OFFSET + PLAT_PHYS_OFFSET -2: .long shmobile_scu_base - PAGE_OFFSET + PLAT_PHYS_OFFSET -ENDPROC(shmobile_secondary_vector_scu) - ENTRY(shmobile_boot_scu) @ r0 = SCU base address mrc p15, 0, r1, c0, c0, 5 @ read MIPDR -- cgit v1.2.1