summaryrefslogtreecommitdiff
path: root/arch/arm/mach-exynos4/cpu.c
diff options
context:
space:
mode:
authorLinus Torvalds <torvalds@linux-foundation.org>2011-07-26 17:41:04 -0700
committerLinus Torvalds <torvalds@linux-foundation.org>2011-07-26 17:41:04 -0700
commit69f1d1a6acbaa7d83ef3f4ee26209c58cd000204 (patch)
tree12be981f8a123b8361edd64b84fd72f339a9655d /arch/arm/mach-exynos4/cpu.c
parent2d86a3f04e345b03d5e429bfe14985ce26bff4dc (diff)
parent1e09939bad24df95ddeeeca4fbec64fa94b66def (diff)
downloadlinux-stable-69f1d1a6acbaa7d83ef3f4ee26209c58cd000204.tar.gz
Merge branch 'next/devel' of ssh://master.kernel.org/pub/scm/linux/kernel/git/arm/linux-arm-soc
* 'next/devel' of ssh://master.kernel.org/pub/scm/linux/kernel/git/arm/linux-arm-soc: (128 commits) ARM: S5P64X0: External Interrupt Support ARM: EXYNOS4: Enable MFC on Samsung NURI ARM: EXYNOS4: Enable MFC on universal_c210 ARM: S5PV210: Enable MFC on Goni ARM: S5P: Add support for MFC device ARM: EXYNOS4: Add support FIMD on SMDKC210 ARM: EXYNOS4: Add platform device and helper functions for FIMD ARM: EXYNOS4: Add resource definition for FIMD ARM: EXYNOS4: Change devname for FIMD clkdev ARM: SAMSUNG: Add IRQ_I2S0 definition ARM: SAMSUNG: Add platform device for idma ARM: EXYNOS4: Add more registers to be saved and restored for PM ARM: EXYNOS4: Add more register addresses of CMU ARM: EXYNOS4: Add platform device for dwmci driver ARM: EXYNOS4: configure rtc-s3c on NURI ARM: EXYNOS4: configure MAX8903 secondary charger on NURI ARM: EXYNOS4: configure ADC on NURI ARM: EXYNOS4: configure MAX17042 fuel gauge on NURI ARM: EXYNOS4: configure regulators and PMIC(MAX8997) on NURI ARM: EXYNOS4: Increase NR_IRQS for devices with more IRQs ... Fix up tons of silly conflicts: - arch/arm/mach-davinci/include/mach/psc.h - arch/arm/mach-exynos4/Kconfig - arch/arm/mach-exynos4/mach-smdkc210.c - arch/arm/mach-exynos4/pm.c - arch/arm/mach-imx/mm-imx1.c - arch/arm/mach-imx/mm-imx21.c - arch/arm/mach-imx/mm-imx25.c - arch/arm/mach-imx/mm-imx27.c - arch/arm/mach-imx/mm-imx31.c - arch/arm/mach-imx/mm-imx35.c - arch/arm/mach-mx5/mm.c - arch/arm/mach-s5pv210/mach-goni.c - arch/arm/mm/Kconfig
Diffstat (limited to 'arch/arm/mach-exynos4/cpu.c')
-rw-r--r--arch/arm/mach-exynos4/cpu.c39
1 files changed, 29 insertions, 10 deletions
diff --git a/arch/arm/mach-exynos4/cpu.c b/arch/arm/mach-exynos4/cpu.c
index bfd621460abf..2d8a40c9e6e5 100644
--- a/arch/arm/mach-exynos4/cpu.c
+++ b/arch/arm/mach-exynos4/cpu.c
@@ -16,12 +16,16 @@
#include <asm/proc-fns.h>
#include <asm/hardware/cache-l2x0.h>
+#include <asm/hardware/gic.h>
#include <plat/cpu.h>
#include <plat/clock.h>
+#include <plat/devs.h>
#include <plat/exynos4.h>
+#include <plat/adc-core.h>
#include <plat/sdhci.h>
#include <plat/devs.h>
+#include <plat/fb-core.h>
#include <plat/fimc-core.h>
#include <plat/iic-core.h>
@@ -103,7 +107,17 @@ static struct map_desc exynos4_iodesc[] __initdata = {
.pfn = __phys_to_pfn(EXYNOS4_PA_HSPHY),
.length = SZ_4K,
.type = MT_DEVICE,
- }
+ }, {
+ .virtual = (unsigned long)S5P_VA_GIC_CPU,
+ .pfn = __phys_to_pfn(EXYNOS4_PA_GIC_CPU),
+ .length = SZ_64K,
+ .type = MT_DEVICE,
+ }, {
+ .virtual = (unsigned long)S5P_VA_GIC_DIST,
+ .pfn = __phys_to_pfn(EXYNOS4_PA_GIC_DIST),
+ .length = SZ_64K,
+ .type = MT_DEVICE,
+ },
};
static void exynos4_idle(void)
@@ -129,6 +143,8 @@ void __init exynos4_map_io(void)
exynos4_default_sdhci2();
exynos4_default_sdhci3();
+ s3c_adc_setname("samsung-adc-v3");
+
s3c_fimc_setname(0, "exynos4-fimc");
s3c_fimc_setname(1, "exynos4-fimc");
s3c_fimc_setname(2, "exynos4-fimc");
@@ -138,6 +154,8 @@ void __init exynos4_map_io(void)
s3c_i2c0_setname("s3c2440-i2c");
s3c_i2c1_setname("s3c2440-i2c");
s3c_i2c2_setname("s3c2440-i2c");
+
+ s5p_fb_setname(0, "exynos4-fb");
}
void __init exynos4_init_clocks(int xtal)
@@ -150,22 +168,23 @@ void __init exynos4_init_clocks(int xtal)
exynos4_setup_clocks();
}
+static void exynos4_gic_irq_eoi(struct irq_data *d)
+{
+ struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
+
+ gic_data->cpu_base = S5P_VA_GIC_CPU +
+ (EXYNOS4_GIC_BANK_OFFSET * smp_processor_id());
+}
+
void __init exynos4_init_irq(void)
{
int irq;
- gic_init(0, IRQ_LOCALTIMER, S5P_VA_GIC_DIST, S5P_VA_GIC_CPU);
+ gic_init(0, IRQ_SPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU);
+ gic_arch_extn.irq_eoi = exynos4_gic_irq_eoi;
for (irq = 0; irq < MAX_COMBINER_NR; irq++) {
- /*
- * From SPI(0) to SPI(39) and SPI(51), SPI(53) are
- * connected to the interrupt combiner. These irqs
- * should be initialized to support cascade interrupt.
- */
- if ((irq >= 40) && !(irq == 51) && !(irq == 53))
- continue;
-
combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
COMBINER_IRQ(irq, 0));
combiner_cascade_irq(irq, IRQ_SPI(irq));