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| author | Ben Dooks <ben.dooks@codethink.co.uk> | 2013-02-01 16:23:08 +0100 |
|---|---|---|
| committer | Ben Dooks <ben.dooks@codethink.co.uk> | 2013-07-01 11:25:33 +0100 |
| commit | fdc3c90513b00e94ee636c11f0da9a8b5d33ebd0 (patch) | |
| tree | 08388ef35abb41ca150c6d2366cf4c65a4f05843 | |
| parent | 2be93ee24c1aa2a5abbcedf5687e28b4def78ffa (diff) | |
| download | linux-fdc3c90513b00e94ee636c11f0da9a8b5d33ebd0.tar.gz | |
ARM: fixup_pv_table bug when CPU_ENDIAN_BE8
The fixup_pv_table assumes that the instructions are in the same
endian configuration as the data, but when the CPU is running in
BE8 the instructions stay in little-endian format.
Make sure if CONFIG_CPU_ENDIAN_BE8 is set that we do all the
alterations to the instructions taking in to account the LDR/STR
will be swapping the data endian-ness.
Since the code is only modifying a byte, we avoid dual-swapping
the data, and just change the bits we clear and ORR in.
Note, not tested against an actual bug, it looked wrong.
Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
| -rw-r--r-- | arch/arm/kernel/head.S | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S index 8bac553fe213..56ddd47fefb9 100644 --- a/arch/arm/kernel/head.S +++ b/arch/arm/kernel/head.S @@ -594,8 +594,14 @@ __fixup_a_pv_table: #else b 2f 1: ldr ip, [r7, r3] +#ifdef CONFIG_CPU_ENDIAN_BE8 + @ in BE8, we load data in BE, but instructions still in LE + bic ip, ip, #0xff000000 + orr ip, ip, r6, lsl#24 +#else bic ip, ip, #0x000000ff orr ip, ip, r6 @ mask in offset bits 31-24 +#endif str ip, [r7, r3] 2: cmp r4, r5 ldrcc r7, [r4], #4 @ use branch for delay slot |