drm/vc4: Flush the CPU cache before firing off command lists.

Signed-off-by: Eric Anholt <eric@anholt.net>

1 files changed, 10 insertions, 0 deletions

diff --git a/drivers/gpu/drm/vc4/vc4_gem.c b/drivers/gpu/drm/vc4/vc4_gem.c
index 940807988f40..5b791b88b5fc 100644
--- a/drivers/gpu/drm/vc4/vc4_gem.c
+++ b/drivers/gpu/drm/vc4/vc4_gem.c
@@ -182,6 +182,10 @@ vc4_flush_caches(struct drm_device *dev)
 {
 	struct vc4_dev *vc4 = to_vc4_dev(dev);
 
+	/* Flush the GPU L2 caches.  These caches sit on top of system
+	 * L3 (the 128kb or so shared with the CPU), and are
+	 * non-allocating in the L3.
+	 */
 	V3D_WRITE(V3D_L2CACTL,
 		  V3D_L2CACTL_L2CCLR);
 
@@ -191,6 +195,12 @@ vc4_flush_caches(struct drm_device *dev)
 		  VC4_SET_FIELD(0xf, V3D_SLCACTL_UCC) |
 		  VC4_SET_FIELD(0xf, V3D_SLCACTL_ICC));
 
+	/* Flush the CPU L1/L2 caches.  Since the GPU reads from L3
+	 * don't snoop up the L1/L2, we have to either do this or
+	 * manually clflush the cachelines we (and userspace) dirtied.
+	 */
+	flush_cache_all();
+
 	barrier();
 }